I've created a schematic and layout of a simple cell using IC6.1.0 and trying to perform DIVA LVS by invoking it from the Virtuoso Layout L window by selecting Verify->LVS...
I am getting an error that I think signifies that the layout is failing to netlist. Please see attached figure showing output error log.
Any help you can provide would be appreciated.
Hi SaulFrom the snapshot, I am guessing that you are using IC611 which is an extremely out-dated version of Virtuoso. Would you please try using the latest version of IC615 to see if the layout netlisting can be completed successfully?Best regardsQuek