I just started using veriloga and have a simple question. Is it possible to assign hex numbers to integers in veriloga ( like you do in C with "int a = 0x0123") ? Couldn't find this anywhere in the veriloga documentation..
In spectre this isn't supported (you can't use even binary constants such as 1'b1 either).
In AMS Designer however, this is support by virtue of it being supported in Verilog. The syntax is something like 'h0123 or 16'h0123 (the first is "unsized" and the second form is 16 bits wide).
In reply to Andrew Beckett:
Ok, thanks for the answer!
I meant to say that in AMS Designer it is supported for VerilogAMS views - so it's supported in VerilogAMS, not VerilogA. I checked in the VerilogAMS LRM and it's unclear whether such syntax is supposed to be supported in the Analog subset of VerilogAMS.