I've a layout for a design with the following grid settings in the Layout editor:
Minor Spacing=0.001; Major Spacing=0.01;X Snap Spacing=0.001; Y Snap Spacing=0.001. The LEF file thus generated has all co-ordinates for the layer shapes with a precision of 1/1000 th of a micro meter (1 nm) (for eq X.XXX um) . However, the header lef from the foundry specifies the Manufacturing Grid resolution to be 0.01 um. This is a conflict and thus I'm not able to integrated the design in SOC encounter since the boundary of the shapes does not fall in the specified grid.
The layout is quite large and not feasible to manually re-shape all the nets and shapes to match the required 0.01 um grid resolution. Hence is there any other way to automatically force the shape boundary (which now has a precision like X.XXX um) to be compatible with 0.01 um grid resolution.(with a precision of X.XX um)?
Tool version= IC22.214.171.1240.12
Assura = 4.1_USR2_HF2
SOC encounter = 6.2
Any help is appreciated.
I can only think of 2 ways at the moment:
1. Go through your existing layouts with SKILL and round-up/down all geometric information
This is a bit dangerous because it could create opens/shorts due to the rounding process
2. Use VLM (or the optimizer) to perform grid-snapping. (use DRC-fix mode)
This will actually make sure that any snapping does not violate the netlist (and remain DRC correct).
But it could also take some time, depending on the size and complexity of the layouts.
The second alternative may requires some tech-file setup as well. It all depends what info you have in your techlib.
Check the docs for "Virtuoso Layout Migrate" to see if you think this may help.
In reply to ColinSutlieff:
The 1st method worked quite well for me and I was lucky not to have any short/open after runing a script to force all boundaries to a given grid setting.
I appologise for the late acknowledgement.
In reply to Debajit B: