hi,i have defined a capacitor using the following statement v(p,n)<+ C*ddt(V(p,n)) in veriloga. I found that this does model the behavior of a capacitor but the spectre simulator doesnt recognize this as a physical capacitor at that node. (It doesnt show the capacitance value in captab). Is there some other way of modeling a capacitor thanks,Anisha
Probably you should report this to customer support - I suspect we need to add some support for an attribute so that the expression can be identified as being a capacitor.As a workaround, you could instantiate a primitive capacitor using a structural instantiation within the Verilog-A. i..ecapacitor #(.c(C)) C1(p,n);Regards,Andrew.