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The Cadence Cerebrus Intelligent Chip Explorer has enabled a revolution in chip design productivity. It delivers better power, performance, and area (PPA) for the chip design process, allowing engineering teams to implement the increasingly large and complex SoCs required by autonomous vehicles, IoT-driven products, the latest 5G, and more.
Both Samsung and Renesas have been using Cadence Cerebrus for digital implementation flow. At Samsung, the optimized flow was used internally to validate a new processor node and decrease the time taken in their design process. Additionally, they’ve been able to deliver 8% better power and timing. For Renesas, optimizing the digital implementation flow has resulted in 15% lower power and 10% better performance.
Find out how Samsung and Renesas are designing their chips with Cadence and learn how Cadence Cerebrus is the future of intelligent chip design in these videos:
Learn more about Cadence Cerebrus and the power of AI to forge intelligent design.