Meet Cadence’s ChipStack AI Super Agent

Cadence ChipStack AI Super Agent shifts AI in EDA from helping with individual tasks to coordinating a connected, evidence-driven design-and-verification workflow, with engineers remaining accountable for the final engineering decision.

Every stage of front-end design and verification produces information that the next stage depends on: specifications shape RTL, RTL informs verification plans and testbenches, and simulation, formal analysis, coverage, and debug results determine what happens next. Yet much of this workflow still depends on how well context travels across tools and activities, how quickly the latest evidence is interpreted, and how the next step is coordinated.

Traditional optimization AI can speed up individual tasks, but faster tasks alone do not create a connected engineering workflow. The larger opportunity is to preserve design intent across activities and let the outcome of one operation guide the next.

The Cadence ChipStack AI Super Agent is built for that opportunity. It applies agentic orchestration to front-end design and verification, using a shared mental model of the design and multiple specialized AI agents that work across Cadence EDA technologies. Around a single engineering objective, it orchestrates RTL generation, verification planning, tool execution, analysis, debug, and iteration, while engineers inspect the generated artifacts and tool results and guide the work as needed.

Where Engineering Time Goes Between Design and Verification

Every new generation of silicon brings greater design complexity and increases the effort required to verify that it functions as intended. Although EDA tools automate many individual tasks, engineers still spend considerable time connecting those tasks and deciding what to do next.

Traditional EDA automation is effective when the task and its execution path are already defined: run a regression, execute a formal proof, analyze coverage, generate a report, or investigate a failure. The challenge often lies between these tasks. Engineers must interpret results, correlate findings across tools, determine whether an issue originates in the RTL, testbench, or verification assumptions, and decide which analysis or action will move the process forward.

This coordination is further complicated by the breadth of capabilities available in modern EDA tools. Identifying the right combination of analyses and applying them in the right sequence can require substantial expertise and effort, particularly as design complexity grows.

The ChipStack AI Super Agent is designed to address this coordination challenge by connecting design and verification activities through a shared understanding of design intent and verification context. Rather than treating each task in isolation, it coordinates relevant workflows, uses intermediate results to guide subsequent actions, and helps engineers move from an initial objective toward evidence-backed results. Engineers remain responsible for evaluating the findings, making engineering decisions, and approving the outcome.

Giving the Agent the Same Design Understanding You Have

An experienced engineer does not read the first sentence of a specification and start coding. They absorb the whole specification, form an understanding of the design intent, and only then write the design or the testbench. The ChipStack AI Super Agent follows the same principle through its mental model.

The agent builds a design-specific mental model from the engineering inputs available to the workflow, which can include specifications, user prompts, existing RTL, testbenches, block diagrams, and behavioral models. It organizes that information into a structured representation of the design intent, hierarchy, functionality, and relationships.

When only a specification is available, the agent builds its understanding from that source. When RTL and testbenches also exist, Cadence technologies ground the model in the implemented design. For example, Jasper can read the RTL to understand its connectivity, and Xcelium can parse the design and testbench to understand the existing verification capability.

Because the mental model captures both the stated intent and the implementation, it can expose problems before any simulation runs. If the specification states that an output port should be driven to a specific value on reset but the RTL does not do so, comparing the two directly reveals the inconsistency.

That shared understanding is then reused across verification planning, formal-environment creation, UVM testbench development, and analysis of verification results, so no activity has to interpret the design independently. Combined with specialized Cadence skills and deep integration with Cadence EDA technologies, the mental model gives the agent tool capabilities and engineering context that a general-purpose coding agent does not inherently possess.

One Objective, End to End

Consider an engineer who gives the ChipStack AI Super Agent a single request: "Help me verify this new RTL meets my specification, fix minor errors, and return coverage metrics." The inputs are the RTL and the specification. Here is how that request moves through the workflow:

1. Understand. The mental model agent elaborates the design (hierarchy, connectivity, parameters), enriches it (functionality, interfaces, protocols), and reasons over it to capture design intent.
2. Review and refine. The engineer can review the mental model and the resulting test plan, and refine each through conversation with the agent before execution. Many customers currently get the most value from this iterative way of working.
3. Plan and build the environments. For formal analysis, this includes a formal test plan, assertions, assumptions, and run scripts. For simulation, it includes a feature-based test plan with coverage goals, and the UVM sequences, monitors, and coverage needed to run it.
4. Execute. A unit-test agent simulates chip behavior using Xcelium Logic Simulation, and a formal agent verifies design compliance using Jasper Formal Verification.
5. Return evidence. Execution produces bug reports and log files.
6. Fix. The RTL agent rewrites the code to address the issues found.
7. Report. The super agent orchestrates the loop and returns the updated RTL with coverage metrics: proof core, cone-of-influence (COI) coverage, functional coverage, and code coverage.
8. Decide. The engineer reviews the RTL, the coverage, and any unresolved issues, and retains final signoff.

Throughout the loop, a proposed fix is an engineering artifact, not evidence of correctness. The relevant Cadence solution analyzes each change, and the resulting formal, simulation, coverage, and debug evidence must be reviewed.

The same pattern applies at the regression level. An engineer can ask the agent to review an entire regression, cluster the issues, and fix them. The agent uses Verisium Manager to cluster failures and rank them by error signature, uses Verisium Debug to trace drivers and analyze the root cause, and then proposes fixes, applies them to the UVM testbench, and iterates.

In short, the workflow runs: Engineering Objective → Mental Model → Agent Reasoning → EDA Tool Orchestration → Analysis and Feedback → Iteration → Verified Outcome.

In one example, Cadence reports that agents running hundreds of dynamic simulations with Xcelium Logic Simulation and Jasper Formal Verification delivered RTL validation cycles that were over 40X faster, cutting a typical five-week verification loop to less than a day. That result applies to a specific portion of the verification of one IP block, not to end-to-end chip design.

Where You Stay in Control

Cadence has announced Level-5 autonomy for the ChipStack AI Super Agent. Rather than relying on step-by-step prompts, the agent evaluates intermediate results, determines next actions, and iterates toward closure across tasks such as specification understanding, RTL generation, verification planning, formal analysis, simulation, debug, and design convergence. Engineers inspect, guide, and collaborate as needed, shifting from executing individual tasks to supervising outcomes and guiding intent, and they retain final signoff.

Native integration with collaboration environments and compatibility with tools like Codex or Claude Code provide transparency into autonomous activity, helping teams stay connected to the system’s progress and decisions. Teams can choose a fully autonomous flow or the iterative approach described above.

Because engineering flows vary significantly across organizations, the ChipStack AI Super Agent also supports customer-defined skills and adaptations to existing methodologies, wrappers, and tool environments. Teams can incorporate their own engineering practices without reducing the agent to a general-purpose coding interface.

What Cadence Reports

Cadence reports up to 10X productivity improvements across coding designs and testbenches, creating test plans, orchestrating regression testing, debugging, and automatically fixing issues. The over-40X RTL validation speedup described earlier applies only to the specific verification loop in that example.

In the next article, we examine where productivity is lost during EDA tool execution and how coordinated, evidence-driven workflows can help teams move more efficiently from a specification change or failure to verification confidence.

Frequently Asked Questions About the Cadence ChipStack AI Super Agent

1. What is the Cadence ChipStack AI Super Agent?

The Cadence ChipStack AI Super Agent is an agentic AI solution for front-end SoC design and verification. It uses a shared mental model and specialized AI agents to coordinate activities such as RTL generation, verification planning, testbench development, regression orchestration, and debug across Cadence EDA technologies.

2. What changes in an engineer's day-to-day workflow?

Instead of manually initiating and coordinating every activity, engineers can define an objective, such as verifying RTL against its specification. The ChipStack AI Super Agent uses the available design context to coordinate the relevant activities, run the tools, analyze results, and determine subsequent actions. Engineers can review and refine the workflow and examine the resulting artifacts and evidence

3. What does Level-5 autonomy mean for the ChipStack AI Super Agent?

Level-5 autonomy enables the ChipStack AI Super Agent to independently execute complex chip design and verification workflows, evaluate intermediate results, determine subsequent actions, and iterate toward the defined objective. Engineers can inspect and guide its activities as needed, while retaining responsibility for engineering decisions, final acceptance, and signoff.

4. Does the ChipStack AI Super Agent replace Xcelium, Jasper, or other Cadence tools?

No. It orchestrates trusted Cadence technologies, such as Xcelium Logic Simulation, Jasper Formal Verification, Verisium Manager, and Verisium Debug, around a defined objective. Simulation, formal analysis, coverage, and debug results remain the evidence used to evaluate the work.

5. Does the ChipStack AI Super Agent support cloud-based and on-premises models?

Yes, ChipStack AI Super Agent flexibly supports cloud-based and on-premises frontier models, including open and cloud-hosted models, to improve designer productivity. This continues the fulfillment of the vision of a true “silicon agent,” spanning the many disciplines and workflows needed to deliver the next generation of intelligent devices.

6. Who owns the mental model?

The mental model is customer-specific, resides on the customer's premises, and can be reused across sessions. It is not stored or owned by Cadence. Customers should refer to the approved product documentation for the applicable data-handling and deployment details.

Explore the Cadence ChipStack AI Super Agent