Analog and Digital IC Design Flows: The Past, Present, and Future of Electronics

                                                                                                                                             This post has been authored by Salagrama Vishnu Teja and Pamula Sai Srinivas

In the ever-evolving world of technology, Integrated Circuits (ICs) are the unsung heroes. From the smartphone in your pocket to the sophisticated systems in autonomous vehicles, ICs are at the heart of modern electronics. But what makes these tiny chips so powerful? The answer lies within the sophisticated relationship between analog and digital integrated circuit design. Let's dive into this fascinating world and explore how these two design flows combine to create the magic we rely on daily. The demand for smarter, faster, and more efficient electronic systems is skyrocketing in today's hyperconnected world. At the heart of this evolution lies the seamless integration of analog and digital design flows—a synergy that powers everything from smartphones and wearables to autonomous vehicles and industrial automation.

Analog design brings the real world into the chip. It deals with continuous signals—voltages, currents, and frequencies—capturing sound, light, temperature, and motion nuances. On the other hand, digital design excels at processing, storing, and transmitting data with precision and scalability.

When these two domains converge in a mixed-signal IC, magic happens. However, designing such systems is no small feat. It requires robust, collaborative flows that allow analog and digital teams to work in harmony, from specification to physical layout and verification. Figure 1 shows an example of an IC with analog and digital blocks. The primary objective of IC design is to perform a specific operation by assembling interconnected circuit elements.

      Figure 1: Example of an integrated circuit

A VLSI engineer will first examine the design specifications and understand the user requirements thoroughly. Then, according to the requirements, the IC will be designed, starting with the initial creation of the top-level SoC architecture. The architecture is depicted in Figure 1 (note that the analog and digital blocks do not always partition symmetrically within the chip; their arrangement will vary based on the logic depth, IO pads, etc.), where the teams will split based on the blocks, which are mainly classified into analog and digital; some blocks are mixed-signal, RF Design, and so on. However, this article focuses only on the fundamental structures of analog and digital domains. After partitioning the chip, the analog and digital teams should follow their respective flows to design their blocks using the standard flow diagrams in Figure 2.

Flows play an essential role in designing ICs. These consist of several stages, depending on the IC type being designed. Each stage must be carefully managed to ensure that the final product functions as intended. Proper planning and adherence to the design flow can significantly influence the performance, power consumption, and area of the IC. The analog and digital design flows are divided into front-end (FE) and back-end (BE) stages, with FE focusing on logic and circuit design and BE addressing physical implementation and layout. Seamless collaboration between the FE and BE teams ensures the efficient integration of functional and physical aspects, ultimately delivering optimized IC designs.

                                      Figure 2: Analog and digital IC flows                            

Analog IC Design Flow

The analog design process begins with selecting the optimal architecture for the macro-function, which is then divided into smaller blocks with defined performance specs and assigned to engineers. The design flow is managed using Virtuoso Studio, a comprehensive suite of tools used for analog design, integrating various simulation and physical verification capabilities to streamline the design flow.

Key components of the flow include:

• Schematic design: Created early with multiple abstraction levels and pin-accurate interfaces for system-level verification. Engineers explore architecture and design schematics using Virtuoso Schematic Editor
• Test bench: An effective verification approach involves developing resilient test benches for analog blocks that remain applicable throughout every stage of the design cycle
• Pre-layout simulation: Ensures functionality and performance under various conditions, according to the design spec using the Spectre Circuit Simulator, which can be integrated with Virtuoso Studio
• Layout design: The goal of layout design is to create a physical layout according to the schematic. We use Virtuoso Layout Suite for this purpose
• Physical verification: Performed using Pegasus Verification System tool to ensure layout compliance and correctness with LVS and DRC checks
• Parasitic extraction: Once the block layout is completed and validated through DRC and LVS checks, we use Quantus Extraction Solution to extract RC parasitics and generate an updated design that includes parasitics. This design is then re-verified using the original test bench with pre-layout simulation
• Post-layout simulation: Verify the functionality of the final layout by simulating and ensuring the results meet design specifications so the layout is ready to tapeout

To deepen your understanding of the Analog IC design flow using the latest Cadence products, we invite you to register for the Cadence Analog IC Design Flow course on our ASK Portal. This course offers valuable insights and hands-on experience to enhance your skills in the complete analog IC flow.

You can earn a Digital Badge for the training mentioned above.

You can also check out the Training Bytes Channel to see the demo videos, from designing a circuit to creating the final GDSII layout.

A variety of courses tailored to each software for every stage of the analog flow are available online. You can explore them through the Learning maps (you can also find the course and badges related to the mixed-signal domain), and each course also offers individual badges upon completion.

Digital IC Design Flow

The digital design flow begins with detailed specifications, a procedural process that involves quickly converting specifications and features into digital blocks and then further into logic circuits. Many of the constraints and the library files associated with digital IC design come from the foundry process and technological limitations. The digital design flow incorporates various software tools at each stage, and this process entails TCL scripting throughout multiple stages of the flow.

The digital flow is a series of steps that an engineer follows in designing and implementing the digital circuits (To learn more, you will find online courses for each stage of the flow here), but here are a few main stages of the flow listed below:

• RTL design: In this stage, the register transfer logic (RTL) is designed using HDL Language (Verilog or VHDL) to describe the behavior of the digital circuit
• Functional verification: The process of ensuring that a digital design behaves according to its specification through simulations using the Xcelium Logic Simulator. Additionally, Cadence’s Verisium AI-Driven Verification Platform can be used to manage verification tasks, accelerate root cause analysis, and improve verification productivity  
• Logic synthesis: In this stage, the RTL code is converted into a gate-level netlist by doing logic synthesis using the Genus Synthesis Solution
• Physical design: This stage is the process of transforming a digital circuit's logical representation (gate-level netlist) into a physical layout that can be fabricated on silicon. It's a critical phase in the RTL-to-GDSII design flow, bridging the gap between abstract logic and real-world hardware using the Innovus Implementation System
• Timing signoff: This stage ensures that the final layout, routed from the implementation stage, meets timing requirements by performing faster static timing analysis (such as Setup, Hold, etc.) using the Tempus Timing Signoff
• Gate-level simulation: This is the final stage for validating the functionality of a layout design using the Xcelium Logic Simulator. It ensures that the design layout is functionally correct and ready to tapeout.

If you want to dive into the detailed steps of Cadence RTL-to-GDSII Flow, a two-day training is available as an online course on our Support Portal, with recorded lectures, and you can get hands-on experience in each stage by running the labs.

Don't forget to obtain your Digital Badge after completing the training!

There are demo videos in this Training Bytes channel, which are bite-sized videos to help you understand the complete flow steps in each stage. Also, you can learn from this 45-minute webinar that covers the complete flow. Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

A variety of courses tailored to each software for every stage of the digital flow are available online. You can explore them through the Learning maps, and each course also offers an individual badge upon completion.

Additionally, you can find more online courses through the Learning maps for every product, every domain, and every flow, which include the latest technologies such as AIML, Photonics, 3DIC, etc.

Happy Learning!