Come Join Us for a SystemVerilog Real Number Modeling Seminar!

Looking to improve your SystemVerilog? On June 17th, 2020, there’s a webinar going on at 9:00 CEST that can help you out. Come join us for our SystemVerilog Real Number Modeling seminar!

You’ve been using device assertions and checks in your analog simulations for a long time—and if you’re not using SystemVerilog’s Real Number Modeling capabilities to their fullest extent, you might be missing a critical edge. Cadence Training and Solutions Director Tim Pylant is hosting this free, one-hour live webinar to help bring you up to speed. Here, he’ll examine how SVA is used to create mixed-signal assertions and how those can be recycled across both the behavioral and circuit-level verification steps. If you’re a beginner, there’s also an introduction into the SVA language, and a long list of examples on how to make assertions for common analog blocks.

There’s something for everyone in this webinar, so come sign up here!

Here’s the agenda:

• What is an assertion
• Digital assertion
• Analog assertion
• How to access analog values
• Examples of analog/MS assertions
• Assertion reuse from RNM to Spice
• Q&A session