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China Graduate IC Design Contest
Contest Duration: April – August 2018
This is Cadence’s second time supporting the China Graduate IC Design Contest. This contest provided graduate students with the opportunity to develop creative electronics design to be applied to a variety of propositions in the areas of:
In total, 254 teams enrolled in the contest and 148 teams, 600+ graduate students, were invited to attend the final on-site contest from August 11-12, 2018. In order to help the finals run smoothly, Cadence provided EDA tools as well as an application engineer to install the software and provide technical support. The graduates participated in the three-phased competition, which included computer test, defense, and a presentation from the top 13 teams.
Taiwan IC Design Contest
Contest Duration: February – May, 2018
Cadence supported the Taiwan IC Design Contest for the first time this year! 573 teams, 1,093 students, from 38 universities enrolled to participate in this contest. They had to create a full design for one of the five categories:
The finals were held from May 2-4, 2018 and 186 teams, 348 students, were invited to attend. Cadence provided EDA tools and online training for the students to learn the Cadence technology. The winners were honored at the Award Ceremony held on July 17, 2018. Jess Yang, DSG Director, represented Cadence by giving a talk titled “Do We Still Need Hardware IC Design Engineer in The Coming Decades?” in which they encouraged students to join the chip design industry and address the importance of EDA in their design career. This was followed by a Q&A panel discussion.
Cadence Academic Network was honored to be a part of this year’s contests and impressed by the innovative designs of the competitors. We look forward to supporting more APAC IC Design Contests in the years to come.