Cadence Academic Network Blogs

Cadence has quite a long history of releasing Generic PDKs for demonstration purposes. All Rapid Adoption Kits (RAKs) are based on one of the GPDKs, which are downloadable from support.cadence.com. For academic users, GPDK has the pleasant side effect that these PDKs can be used for education, with no extra NDAs to be signed. The designs are non-manufacturable, but the device models, technology rules and PCells are close enough to their manufacturable counterparts from industry-grade PDKs, so that the electrical effects and design flows are basically the same.

Cadence recently  released version 1.1 of the Advanced Nodes GPDK cds_ff_mpt, where ff stands for FinFET and mpt for multi-patterning. This PDK has been used by students and professors to understand and model the new challenges that are present in the design for advanced nodes. As an example FinFET transistors have only discrete fin width, many more parasitic elements needs to be taken into account, multipatterning requires new layout styles with avoidance of loop violation, where the shapes cannot be decomposed to two different masks. All these effects could be reproduced with the initial version of the Advanced Nodes GPDK. This PDK also supports features like parasitics extraction, support for mixed-signal design, interactive highlighting of potential electromigration violations (EAD), which are becoming increasingly important in advanced nodes, interactive DRC, DFM fill, support of chaining and folding for stacked devices and more.

The version 1.1 release provides a „lef“ directory, with a tech-lef and a standard cell lef. This library currently consists of a limited number of cells, , to enable experimentation and an inclined reader could as an exercise create additional cells. However, the library as it stands should enable researchers and students to gain experience with a majority of the technical challenges one would encounter down to 3nm.

One restriction that an analog designer has to face when designing for advanced nodes is the regularity of the layouts, due to multipatterning no false direction routings or off-grid routings are possible. All analog devices must be placed in rows, similar to digital standard cells. There is a Rapid Adoption Kit available „Row-based Placement“, which demonstrates placement of analog and custom digital cells as well as filling up the rows with corresponding filler cells.

Another important concept is called Width Spacing Pattern (WSP), which is for defining track pattern that consist of different width and spacing values for wires. RAK „Automated Device-Level Placement and Routing Flow for Advanced Nodes“ explains the whole automated placement and routing design flow (APR) for analog devices. Finally the RAK „WSP-Based Power Grid Generation for Advanced Node“ demonstrates power routing.

Cadence enhances the ADVGPDK as new Virtuoso tools and features are introduced.  We welcome feedback on tool and feature support as well as topics for future RAKs.