Genus Synthesis Solution 15.2 Now Available to Academia

To support academia using the latest industry-standard tools, Cadence's Genus Synthesis Solution has been made available to universities. If you want to use the Genus solution, please contact the Cadence university partner in your region or write an email to academicnetwork@cadence.com. The Genus solution-based Rapid Adaption Kits and iLS courses are also available through Cadence university partners including distributors such as Europractice.

The ultimate goal of the Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR) in final implementation. The new massively parallel architecture delivers up to 5X faster synthesis turnaround times whilst a new physically aware context-generation capability reduces iterations between unit- and chip-level synthesis by 2X or more. On top of this, a new global, analytical, architecture-level optimization engine can reduce datapath area by up to 20% without any impact on performance.

• Massively parallel architectures can handle huge designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers
• A simple Tcl command at the end of a chip- or block-level synthesis can be used to “clip” out the full timing and physical context for any subset of a design. These clips can be used to drive unit-level RTL synthesis with full consideration of chip- or block-level timing, floorplan, and placement, reducing unit-level iterations required to achieve timing closure by 2X
• The Genus solution shares several common engines with the Innovus Implementation System, including the GigaPlace engine, delay calculation, parasitic extraction, and timing-driven global routing. Timing and wirelength between these integrated tools correlate tightly to within 5% and global routing performance is 4X better
• A new architectural-level power, performance, and area (PPA) algorithm considers a number of possible micro-architectures at critical datapath regions, before solving an analytical model over all datapath regions to achieve the globally best PPA for the design. This can reduce datapath area by up to 20% without any impact on performance
• The Genus solution shares a common user interface with the Innovus and Tempus environments to streamline flow development and simplify user proficiency across a complete Cadence digital flow. The new user interface includes unified database access, MMMC timing configuration and reporting, and low-power design initialization

Learn more about the Genus Synthesis Solution.

Anton Klotz