Get email delivery of the Cadence blog featured here
Zhan Gao studied microelectronics in the Xidian University in China and after getting her master’s degree in developing an algorithm to abstract parasitic capacitors at Chinese Academy of Sciences in Beijing, she chose to continue with research and is currently a PhD candidate in the Eindhoven University of Technology. As a PhD student, Zhan is working on a new project which is initiated by Eindhoven University of Technology and IMEC in cooperation with Cadence Design Systems.
So far, the most commonly used fault models in industrial IC testing are stuck-at and transition, which target the potential faults between library cells in the gate-level netlist as generated by logic synthesis. With CMOS technology scaling, ICs are increasingly prone to defects. Recently, the test community has come to realize that there are many potential defect locations inside library cells, which can also cause circuit malfunction. Therefore, it is necessary to create a new fault model to target the intra-cell defects. Cell-Aware ATPG targets the intra-cell defects by considering the layout-extracted transistor-level implementation of library cells. To detect the defects inside the cells, Cadence PVS/QRC and Liberate/Spectre will be used to find test patterns for all the potential defects of each cell. Then Modus is used to finish the ATPG process for each IC design. Note that, due to the many underlying analog simulations, the assessment for each library cell of the detection capabilities of test patterns is a time-consuming job, this work only needs to be performed once; the results can be reused for all IC designs based on this standard-cell library.
Detecting defects of integrated circuits by observing the internal circuitry of standard cells is the trend with the aggressive CMOS technology scaling. In this project, the collaboration with IMEC provides access to the most advanced CMOS technologies (e.g., 5nm and 3D integration) in the world. Experiments can be done on these new technology libraries, which will provide precious feedback for technology development as well.
Cadence Academic Network is supporting Zhan on her project and wishes her success in getting great results in her research!