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I had an exciting week in July here in Pittsburgh, PA with the IEEE Computer Society Annual Symposium on VLSI (ISVLSI.org). I was fortunate enough to be invited to do one of the keynotes at the Symposium, thanks to the co-chairs: University of Pittsburgh Professor Helen Li and Carnegie Mellon University Professor Xin Li, and my connection to them through the Cadence Academic Network and Cadence Director Patrick Haspel. My normal day as an engineering director in Virtuoso R&D focuses on ensuring our continued incremental and innovative progress in assisted and automated placement and routing for our customers. So taking a few days out to see where the academic research and attention is focused was really enjoyable. There was great diversity at the symposium with attendees from all over the globe and working on many different topics. The variety of topics for the keynotes and panels was really interesting:
Beyond the keynotes and panels, it was clear that the focus of the interesting papers and research was in two non-traditional areas: Nano-scale/post-CMOS devices and non-Von Neumann architectures:
Finally, I was most gratified to have a detailed discussion about how professors and their graduate students are using Virtuoso today, and the need for generic process design kits [GPDKs] for both teaching and research. I was happy to be able to point them to the most recent GPDK release with FinFET enablement in gpdk_ff.
It was a great opportunity to interact with the academic community, and I look forward to the next opportunity.