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In order to describe the purpose of this education kit, let’s leave the EDA turf for a minute and enter the world of computer architecture. If you still remember the 80s, the PCs of that time had one single CPU (Central Processing Unit), which did most of the work. At some point, specialized co-processors were added to support the CPU for specific tasks, like the FPU (Floating Point Unit) for floating-point operations, or the MMU (Memory Management Unit) for memory management. In the 90s, GPUs (Graphic Processing Unit) entered the market and supported the CPU in calculating 3D objects. In the 2010s, together with the multi-core era and better integration, systems became more heterogenous, consisting of many different components optimized for specific tasks. Such optimized components are called accelerators, one example would be the NPU (Neural Processing Unit), which is an accelerator for machine learning algorithms.
There is a huge variety of how and which tasks should be accelerated creating a large design space. A structured DSE (Design Space Exploration) is mandatory to decide if a specific architecture achieves the required goals. The goals are always the same: PPAC (Performance, Power, Area and Costs). The aim of the DSE is to get this valid estimation as soon as possible in the early stages of the design cycle. Tools and methodologies are needed to get these answers.
But how can you measure the PPAC during the design exploration phase to have some preliminary numbers for comparison? This is done by using a Virtual Prototype, so a model of the system written in SystemC and run within a Virtual Prototype environment called Helium Virtual and Hybrid Studio. Within this environment, it is possible to determine the number of cycles which are required for the execution of different parts of the algorithm. Using Cadence Stratus High Level Synthesis, further design space exploration is possible, like introduction of pipelining measuring the improvement of performance versus area growth.
Design Space Optimization using Stratus
This education kit shows three ways to accelerate a machine-learning algorithm, which is supposed to perform on Lenet-5 benchmark. The first way is to run it on an unmodified Tensilica core, which is the most straight forward approach, but possibly not the fastest. The second way is to implement a TIE (Tensilica Instruction Extension) to the Tensilica core, which is accelerating the algorithm by providing some optimized instructions creating an ASIP (Application-specific Instruction Set Processor). This provides a faster approach. The third way is the creation of a dedicated accelerator. It can be efficiently implemented as a SystemC model and connected to the Tensilica core, and be used either in a Virtual Prototype or synthesized to RTL (Register Transfer Level) using Stratus.
The Shift-Left Methodology for the Development of Hardware Accelerators Education Kit consists of six modules with lectures, labs and video recordings. All provided materials are editable and can be easily adapted for the educators’ needs. The students taking this course should have knowledge in C++, SystemC, hardware description languages and computer architecture. All software tools required for the practical part are available through the Cadence University Program. To become a member of the Cadence University Program, please write to email@example.com for assistance. For the practical part on Tensilica, access to Cadence Tensilica University Program is required. In order to become a member of the Tensilica University Program, please fill out and submit an application form or write to firstname.lastname@example.org for assistance.
The Academic Network is excited about adding another education kit to our growing list of Academic Resources. Partnering with academia and business groups is helping educators around the globe to enrich their classroom curriculum. Interested in learning about the other education kits available? Explore our Academic Resources hub.