Spotlight: Cornell Custom Silicon Systems

Written by Daniel Kaminski, Cornell Custom Silicon Systems Full Team Lead/Analog Subteam member, and Vayun Tiwari, Cornell Custom Silicon Systems Digital Physical Design Subteam member

At Cornell University, the Custom Silicon Systems (C2S2) project team is pushing the boundaries of what undergraduates can achieve in semiconductor design. Our team has been building a track record of successful tapeouts, including three consecutive years of silicon, with more to come.

Partnering with the Lab of Ornithology

The project guiding the progress of the team these past few years has been a collaboration with Christopher Tarango, who was working towards a PhD in the Cornell Lab of Ornithology. He discovered the limitations of modern bird tags (audio recording devices) in terms of size, weight, battery life, and functionality, while studying the behavior of Florida Scrub Jays. After some discussion with C2S2, a partnership was formed to attempt to address these issues. The team has continually built towards a proof of concept bird tag system, leveraging the power savings and acceleration capabilities of application specific integrated circuits (ASICs), as compared to general computational silicon (such as microcontrollers), to provide an uplift in performance on all fronts. The team continues to stride towards the completion of such a system.

Originally, the C2S2 workflow was based on open source tools with the SKY130 PDK. When Cadence released a version of the SKY130 PDK for use with Cadence software, C2S2 transitioned to using tools such as Spectre for simulation and verification, Pegasus for DRC and LVS, and Quantus for parasitic extraction. Transitioning our workflow to using Cadence tools both accelerated the analog design cycle and, unbeknownst to C2S2 at the time, poised us for a smoother transition to using the TSMC PDK.

TSMC Pivot

When EFabless shut down earlier this spring, we were faced with a major challenge to pivot to TSMC's 180nm process node, an industry grade node that required us to adopt full industry workflows. This meant unpacking a commercial PDK, setting up new flows, and learning how to use these tools.

Cadence software was at the heart of this transformation. Tools like Virtuoso and Innovus became our key implementation engines. In just 100 days, a group of undergraduates—most of us with little prior exposure to professional design tools—managed to re-implement our designs, build out a working flow, and tape out working silicon.

The Tapeouts

The Analog tapeout contained an 8-bit 4.4MS/s true-differential SAR ADC, in addition to some test structures such as analog switches and a comparator. Cadence tools also allowed the team to explore mixed signal design: the SAR ADC requires an FSM to guide its binary search algorithm. Despite the challenges of designing and verifying a tightly linked feedback loop with digital logic and analog blocks, Spectre AMS accelerated this process by greatly reducing simulation time. This FSM was also implemented using Innovus (for the place and route of standard cells) and then routed to the top level in Virtuoso. Positive results from post-silicon testing of this chip has encouraged C2S2 to continue to explore mixed-signal integration in the future.

Digital's chip takes ADC samples through an asynchronous FIFO and feeds two FFT stages and a simple classifier. We explored LBIST on the second FFT, adding LFSR stimulus and MISR capture to validate that block. A small router and crossbars move data between blocks, and serializers/deserializers handle block I/O. The design synthesizes at 100 MHz. Using Innovus, we built the pad ring for reset/clock and FIFO/SPI pins, then placed and routed the logic with a focus on low power.

RF's chip implemented a 915 MHz on-off keying (OOK) transceiver. The chip integrated several key building blocks, including two low-noise amplifiers (a resistive-shunt LNA and an inductor-degenerated LNA), an LC-tuned voltage-controlled oscillator (VCO), an inverter-based VCO, an envelope detector for OOK demodulation, and a power amplifier. The subteam used Cadence EMX for electromagnetic simulation and modeling of on-chip inductors to ensure accurate high-frequency performance. This was the first RF tapeout on C2S2, marking a major milestone in establishing a foundation for future high-frequency designs.

This experience challenged the common assumption that advanced chip design is the domain of only professionals or graduate students. With the right tools, mentorship, and motivation, undergraduates can absolutely deliver quality silicon.

Next Steps

As our partnership with the Cornell Lab of Ornithology comes to a close, C2S2 is turning toward new horizons. We're actively exploring fresh project ideas with new partners, continuing our mission of building impactful silicon systems that connect academic curiosity with real-world applications. Having built a solid foundation through multiple successful tapeouts with the Lab, we are now eager to explore new and ambitious directions. A recent team poll revealed that nearly half of our members are eager to bring machine learning directly onto silicon. At the same time, we want to remain true to our roots in sustainability, ensuring our projects continue to address challenges that matter beyond the lab. This balance, pushing the boundaries of performance while designing responsibly, defines the spirit of our group. Looking ahead, members are excited to pursue designs that integrate mixed-signal functionality, on-chip SRAM memory, and other advanced features. These directions open the door to new architectures and capabilities that will stretch both our technical skills and creativity.

Through all of this, Cadence software will remain central to our journey. Whether it's Virtuoso for analog and RF design, Innovus for digital implementation, or simulation and verification tools across the flow, Cadence enables us to explore ambitious ideas while ensuring we stay grounded in proven industry practices. With these tools, we can continue transforming student enthusiasm into working silicon.

Learn more about the Cadence Academic Network.