Stratus High-Level Synthesis Is Available to Academia

21 Mar 2016 • 1 minute read

To support academia using the latest industry-standard tools, Cadence's Stratus High-Level Synthesis is now available to universities.

Cadence Stratus High-Level Synthesis (HLS) is the first HLS platform that you can use across your entire system-on-chip (SoC) design. The tool delivers up to 10X better productivity than traditional register-transfer level (RTL) design and reduces the intellectual property (IP) development cycle from months to weeks. With Stratus HLS, you can easily create abstract SystemC, C, or C++ models using the Stratus integrated design environment (IDE) and synthesize optimized hardware from those models. You can then retarget these models to new technology platforms and reuse them more easily than you could traditional hand-coded RTL. With the Stratus IDE, you can actively make tradeoffs between power, area, and performance from within the HLS environment.

Stratus HLS integrates the technologies of Cadence Forte Cynthesizer and Cadence C-to-Silicon Compiler, delivering:

An integrated design and verification flow
Engineering change order (ECO-), low-power, and physically aware design
Customizable floating-point IP
A sixth-generation synthesis core

To gain access, please contact the Cadence university partner in your region, or write an email to academicnetwork@cadence.com. Rapid Adoption Kits for the tool are also available through Cadence university partners, including distributors such as Europractice.