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Since I’ve started working for Cadence Academic Network three years ago, when talking to big Cadence customers sooner or later they mention the verification topic. The need for verification is increasing, the demand for verification experts is rising, but the universities are not really interested in teaching verification. There are several reasons I can think of:
Nevertheless, there are professors and students, who understand the importance of verification in modern hardware design and offer verification courses at universities. Mostly this understanding comes with the demand, if a university is doing large digital designs, then they quickly realize, that they cannot neglect verification. Cadence Academic Network did a survey among these professors in order to understand their motivation, the tools they are using, their experience level and their plans for the future. We got 8 responses from EMEA and US.
Before we dive into the questions, it is clear that the demand for verification engineers is rising, so call-to-action for academia would be to establish more verification courses to train future verification engineers and this survey might help to see, what other universities are concentrating their efforts at.
When asked about the motivation, why professors are teaching functional and formal verification, the answers were about understanding that next generation of engineers in their own country will need to know about verification and the demand in the industry is high.
The second question is about for how long the professors are teaching verification. The majority has just started, between 1-3 years
But the interest from the students is high, the majority of courses have more than 10 students attending the lectures
The majority of the students have an electrical engineering background, but also computer science and computer engineering students are interested in verification
There is a battle going on between SystemVerilog and e proponents. While e is considered to be more newbie friendly and more elegant, engineers who are familiar with SystemVerilog want to stay in their environment and use the same language for modeling and verification. This is shown by the answers to the question on preferred verification language for education.
UVM is the king when it comes to verification methodology. Few universities are also teaching formal, other verification methodologies are far behind.
There are a variety of Cadence tools for verification, most obvious is the digital simulator Incisive, universities only recently got access to our new digital simulator Xcelium, therefore it is not yet in the list, but also our formal verification tool JasperGold and verification planner tool vManager are used.
Most of the difficulties in teaching come from steep learning curve for both professors and students
But Cadence is helping with different materials and professors are using it for their lectures
When asked about the future efforts in the field of verification most wishes were towards automation, integration and efficiency increase
For the full version of the survey and further questions how Cadence Academic Network is helping teaching verification please contact me: firstname.lastname@example.org. We are always looking for more we are looking for more universities we can work with to further strengthen the footprint of verification education in academia!