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What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

21 Jun 2016 • 2 minute read

CAN_logoIEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting and discussing scientific trends, emerging results, hot topics and applications in the area of electronic-based circuits and system testing. ETS’16 which took place from the 24th to the 27th of May, was the 21st occasion of the symposium and was held in Amsterdam, the Netherlands. The event was organised by the Delft University of Technology, which co-sponsors the event along with the IEEE Council of Electronic Design Automation (CEDA).

The symposium’s technical program consisted of three plenary keynote addresses, eight technical and scientific sessions, four embedded tutorials, two special sessions on emerging test solutions, one panel, five vendor sessions and three poster sessions. ETS acceptance ratio was only 22%, which is a further indication of the quality of the articles presented. There were about 200 attendees from industry, research institutes and universities alike. Cadence had two presentations in two separate vendor sessions: Daniel Bayer from the WFO team in Munich presented Cadence solution on Ethernet Verification IP for automotive applications within ISO 26262 (vendor session: EDA for automotive) and Vladimir Zivkovic presented mixed-signal test implementation using Modus tool to implement emerging IEEE 1687 standard on Sierra using embedded design-for-test instrumentation, co-authored with a number of colleagues from both IPG and R&D (vendor session: Mixed-Signal and RF Test). 

Here are the key take away points from the conference:

  • Products will adapt themselves to process variation, circuit margins, environmental changes and aging – thereby simplifying testing and achieving superior fault tolerance as well as power and performance. Testing will be viewed more as a production personalization and data collection process (driving fab/design improvements) rather than just sorting pass/failing dies.
  • EDA efforts are being made towards analog fault simulation and test generation, as well as an IEEE 1687 extension towards the analog domain.
  • Digital test is almost contained and is not considered a major factor in test cost or NRE for test, as is mixed-signal test. Mixed-signal tests are loop-back based margining tests and had been broadly adopted in the past, because they can test most High-Speed IO functionality without requiring costly ATE platforms. The DFT based on loop-back tests verifies device performance in five areas: transmitter at functional speed, receiver at functional speed, receiver jitter tolerance, receiver minimum detectable level, and transmitter implied jitter generation.
  • To ensure manufacturing test quality and high reliability for IoTs, DfT designers need to use new test and repair solutions to enable power reduction during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access.
  • As Advanced Driver Assistance Systems (ADAS) in cars becomes a reality, more electronic applications in the automotive space require online testing. These are safety critical applications, so there must be some type of online testing available for the processors implemented in these systems.
  • Increased testing on-chip, reduced usage of ATE and test cost cause a major bottleneck. Since digital test is more or less contained, the main challenge is the analog/mixed-signal and the RF portions.


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