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People are adopting more and more technologies like AI into their lives. New intelligent devices are fueling growth in our economy. Meanwhile, there’s a huge talent gap of highly trained or even entry-level electronic engineers to design next-generation products. Engineers are being asked to do more, speed up design cycles, and invent more innovative products than ever before.
By employing generative AI in its tools for the design of chips, boards, and systems, Cadence has increased designer productivity – in some cases, by up to 10X. This can have a profound impact on this engineering shortage.
The CHIPs and Science Act, which funded $53 billion for domestic chip manufacturing and research, is expected to create tens of thousands of electrical engineering jobs. According to Kiplinger research, the US needs to produce more EE college graduates to meet these requirements, and the outlook is bleak. It appears that computer science is dominating the mindshare of students looking into engineering-related careers, which is a massive problem for the electronics industry.
Estimates are as high as 50,000 new semiconductor engineers are required over the next five years for all the new factories and research projects companies are planning to build with subsidies from the Chips and Science Act. This challenge is compounded by the fact that an aging generation of engineers is preparing to retire without a sufficient supply of younger-generation trained engineers to take over. The expected return on investment in the CHIPs and Science Act might just not be there if there aren’t enough engineers.
Companies can’t escape the challenge of being first to market with innovative new products with higher levels of performance in a smaller area and with lower power demands. This increasing design complexity not only requires more engineering talent but also raises the requirements for extensive verification and testing. Chip design gets exponentially harder as transistors get smaller, and this complexity is making the design engineer shortage even worse.
As the chip design industry moves from 5nm design to 3nm and 2nm in the years ahead, the verification workload, in particular, is increasing. Industry estimates are that verification costs from a 7nm design average $223.3 million, for a 5nm design average $463.3 million, and for 3nm will boom to $650 million. With these expenses, chip companies cannot afford to get anything wrong in their design cycle!
The electronic design industry has moved to higher levels of abstraction and improved designer productivity over the years. Generative AI has the potential to leapfrog all of these productivity increases by analyzing huge data streams, identifying problem areas, and making recommendations, guiding engineers to the best possible solutions.
Cadence’s customers are realizing amazing results by applying generative AI techniques to improve designer productivity. Generative AI significantly impacts three main categories, as shown in Figure 1, below.
Figure 1. Generative AI has a big dollar effect on your design
Generative AI enables designers to create new designs with less effort, quickly make tradeoffs for the best power, performance, and area (PPA), and do much more with less, particularly for efficiency in verification. And most importantly, it allows companies to design quicker with fewer engineers. In many cases, more junior engineers can perform tasks that previously required senior engineers because the tools guide the design experience.
While the solution to needing more designers is to use AI and generative AI techniques to improve productivity, AI requires large amounts of data for training, and every year, that amount of data goes up. Analyzing that data requires the most experienced engineering talent and, frankly, has become just about impossible because of the quantity of that data.
One of Cadence’s most significant AI innovations has been its Cadence Joint Enterprise Data and AI (JedAI) Platform, which enables a considerable productivity shift from single-run, single-engine algorithms to the optimization of multiple runs of multiple engines across a design and verification flow. The Cadence JedAI platform enables engineers to glean actionable intelligence from massive volumes of chip design and verification data, dramatically improving engineering productivity while dramatically improving power, performance, and area (PPA). This includes design data, RTL, netlist, waveforms, workflow data, runtime, memory usage, disk space usage, and more information than any one design engineer could ever absorb.
The JedAI platform lets design teams at Cadence customers learn from and build on design expertise, creating a robust database that will improve productivity over time. More junior engineers will be able to glean knowledge from this database, saving valuable time on the learning curve and becoming more productive and quicker.
Verification is an essential but very time-consuming task of checking all the possible design issues, finding the bugs, and fixing them. In addition, it’s one of the most unrewarding engineering tasks because it is so repetitive and challenging. By employing generative AI throughout the verification process, the entire process can be speeded up, and accuracy can be increased.
Because verification is a complex, multi-step process using multiple engines, Cadence designed the Verisium AI-Driven Platform, which leverages big data and AI across multiple runs of the multiple engines throughout an entire SoC verification campaign. Generative AI helps engineers achieve the same coverage with significantly fewer cycles and find more bugs without creating new ones (which often happens when fixing bugs). The Verisium platform optimizes verification workloads, boosts coverage, and accelerates root-cause analysis of bugs.
Figure 2. The Verisium AI-driven verification platform makes the entire verification process much more efficient, reducing the total number of engineers required.
Cadence significantly reduces the time it takes to design and optimize a chip for the best power, performance, and area tradeoffs through its Cerebrus AI-driven tool. Cadence Cerebrus significantly reduces design time while improving overall quality. Using Cadence Cerebrus, customers have seen up to 60% improvement in timing and lower leakage by nearly 40 percent. At the same time, they’ve driven up engineering productivity by up to 10X.
Cadence has employed AI techniques throughout its entire design tool suite, making chip design productivity increases become real in actual designs.
Cadence has also applied AI techniques to its printed circuit board (PCB) tools. Allegro X AI automates the placement and routing of components on PCBs, reducing design time from days to minutes and improving design quality. This has the same effect as substantially increasing design teams with talent that is, unfortunately, hard or impossible to find.
Allegro X is already revolutionizing the way PCBs are designed, saving valuable designer resources.
Designers can efficiently and intelligently explore 3D electromagnetic (EM) and high-speed signal and power integrity designs using generative AI technology. Cadence Optimality Explorer removes the need for exhaustive sweeps and dramatically reduces the number of iterations required to converge to the optimized solutions. Optimality Explorer delivers optimized designs on average 10X faster than traditional methods, with up to a 100X speedup realized on some designs.
Because of the engineering shortage, Cadence will continue to invest in employing generative AI techniques in its design tools. Generative AI is far from taking over the entire design process, but it is letting companies create much better designs faster, with fewer engineers. Cadence’s AI journey is well underway, yet still in its infancy as new techniques are developed to make designers more productive than ever before. Junior engineers will be able to take on more complex tasks as the computer programs they use to generate designs lead them to a quick understanding of many of the things senior engineers have learned.