Industry’s First UALink-200G Controller and PHY Running in 3nm!

AI systems are running into a familiar problem. Compute keeps scaling, but the infrastructure connecting that compute is starting to dominate system behavior. Interconnect latency, bandwidth efficiency, and power now have as much impact on performance as the accelerators themselves. Cadence is proud to announce the industry's first UALink‑200G controller and PHY running in 3nm—a milestone that reflects a real shift in how AI systems are being architected, not just an incremental speed increase.

As models get larger and accelerator counts increase, scaling stops being linear. Moving data becomes harder than processing it. Latency accumulates. Synchronization costs grow. Effective bandwidth drops as more devices contend for the same fabric. Adding accelerators without addressing these effects delivers diminishing returns.

UALink targets this problem directly. It is a memory‑semantic, scale‑up interconnect designed for tightly coupled communication inside a rack or pod. This is not a best‑effort environment. Small variations in latency show up immediately in workload behavior. Protocol overhead matters. Determinism matters. The interconnect has to move data predictably, at low latency, without consuming excessive power. Cadence's UALink implementation is built around these constraints, rather than treating them as secondary concerns.

Cadence's UALink Controller IP implements the full set of UALink v1.0 spec‑derived features required to make large‑scale accelerator fabrics practical and efficient. The controller supports native read, write, atomic, and message transactions, enabling simple load/store semantics that closely map to accelerator programming models. Flexible multi‑furcation modes (1×4, 2×2, and 4×1) and support for both 212.5Gb/s and 106.25Gb/s serial rates allow designers to right‑size bandwidth per endpoint as systems scale. Reliability and efficiency are addressed through programmable FEC interleaving, FEC error‑indication bypass, and built‑in link‑level retry (LLR) with credit‑based flow control (CBFC) across both the transaction and data link layers. Transmitter pacing further reduces unnecessary GPU clocking and power, while comprehensive data‑path protection and SRAM ECC help sustain predictable performance under heavy, highly synchronized AI workloads—exactly the conditions that are challenging for interconnects.

Pushing UALink to 200G per lane sets a new bar for bandwidth density. Doing so with a full controller and PHY in 3nm makes the problem harder. At advanced nodes, inefficiencies are exposed quickly. Power margins shrink. Signal‑integrity challenges increase. Architectural decisions that look reasonable on paper become costly in silicon. Delivering working UALink‑200G silicon at 3nm required tight coupling between protocol design, controller architecture, and PHY implementation—an area where Cadence has long focused its development effort.

What matters most here is not the specification. It's the silicon. A validated UALink‑200G controller and PHY in 3nm from Cadence shows that scale‑up interconnects are not lagging behind leading‑edge compute. They are being developed alongside it. Interconnect is no longer something that gets bolted on after the fact. It is being designed as part of the core system architecture.

This has real consequences for future AI platforms. Accelerator counts will continue to rise, but power budgets will not. Scale‑up fabrics must deliver high effective bandwidth while keeping latency predictable and energy per bit under control. They must integrate cleanly with advanced process nodes and complex packaging. These are baseline requirements now. Cadence's early delivery of UALink‑200G in 3nm shows they can be met in practice, not just in theory.

Industry first reduces uncertainty. They give architects and designers something concrete to plan around. The first UALink‑200G controller and PHY running in 3nm establishes a reference point for what next‑generation scale‑up interconnects need to deliver as AI systems continue to scale.

AI infrastructure will not advance through compute alone. How that compute is connected increasingly defines system limits. Interconnect is no longer background plumbing. It is shaping architecture. Cadence's work on UALink‑200G in 3nm is part of that shift, turning architectural intent into silicon that can actually be deployed.

Learn more about Scale Up vs. Scale Out in Modern AI Factories.