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If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling, meeting power integrity targets, managing voltage drop, and other related challenges. While the solutions aren’t simple, there are emerging techniques that offer some promise. One such technique, according to University of Toronto Professor Farid N. Najm, is constraints generation—a rich area of study involving new ways of thinking about the power grid and power delivery.
Najm, who chairs the university’s Department of Electrical and Computer Engineering, presented an overview of constraints generation and other power-management techniques during his talk on “Managing Design Challenges for Power-Constrained SoCs” last Wednesday (August 19, 2015) at Cadence’s San Jose headquarters.
“Power is a first-order concern, like timing,” said Najm, whose current research work is focused on power grid verification and optimization and on managing the impact of process and environmental variations.
Sharing an overview of his current research, Najm provided a bit of background on the power landscape today. Nowadays, the power grid topology covers all levels of the metal stack, with some 500 million logic cells and their current sources, he noted. In a given chip, many blocks will have their own separate power supply that’s gated, occupying a certain number of metal layers and connected at the top by the global grid. In every layer, the grid is mostly a regular mesh.
Many areas of study focus on power grid verification for voltage integrity, along with grid reliability and power scheduling. Power scheduling accounts for the workload that you can run in an SoC without violating power integrity targets. Looking ahead, noted Najm,“We may be able to develop a query engine so that the power controller can ask, Can I bring this up before I shut this down, or will there be a signal integrity problem?”
In this landscape, the design challenges for power integrity revolve around keeping the power supply regulated, said Najm. Engineers need to watch out for things like voltage drop at the bottom layers and electromigration. “We need grid verification—early, incrementally, and at signoff. The catch is, you don’t know what the circuit is doing,” noted Najm.
How are engineers addressing these challenges?
Simulation is being used for specific scenarios, and there are tools for vectorless verification. However, Najm noted, both options offer limited coverage and optimistic results because they are simulation based.
“The engineering solution from designers is to overdesign,” Najm said. “There’s a lot of pain now on the routing side. Designs take longer to implement because of limited silicon real estate due to overdesign on the grid.”
Said Najm: “There are no tools today to qualify the grid. Is it any good? Can it be improved? How much current does it tolerate? There’s no way to tell how much total current the early grid supports without causing power integrity problems, no way to tell what chip workload patterns are allowed by the candidate grid.”
The dearth of viable solutions has led Najm to constraints-based verification. As Najm explained, in this approach, you’d generate circuit current constraints that, if satisfied by the underlying circuitry, would guarantee power grid safety. This approach would:
Power scheduling presents a potential killer app for constraints generation. The methodology could, for example, lead to a way for a chip’s power controller to check whether a candidate combination of blocks is safe to turn on, or if it this would violate grid voltage targets.
“Constraints generation is possible and practical, and is a rich area of study that was previously unexplored,” said Najm. “It provides quality metrics for the power grid and a rigorous approach for early grid design and planning.”