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Rising test costs can be a real drag on your bottom line. If you’re looking for a way to trim your test costs, take a look at Cadence’s new Modus Test Solution. This DFT technology provides a way to drive compression ratios higher without a subsequent explosion in wirelength. As a result, you get an up to 3X reduction in test time for digital logic without any impact on fault coverage or chip routing resource.
The tool achieves these advantages through its physically aware 2D Elastic Compression architecture. The architecture consists of two main capabilities:
Modus Elastic Compression makes compression logic, including registers and feedback loops, sequential. It's one of the innovations in the Modus Test Solution that enables it to reduce test time by up to 3X and support compression ratios beyond 400X.
The Modus Test Solution includes capabilities for memory BIST, logic BIST, testpoint insertion, and diagnostics. It’s also part of Cadence’s full-flow digital solution, so you’ll get a common, unified UI for Tcl scripting and reporting.
Get the datasheet and other resources about the Modus Test Solution from this page, and learn how this new technology can help you lower your test costs.