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At 10nm, design tasks that were once optional have become mandatory. Take coloring, for example—shrinking processes have required a transition from a route-driven implementation to a color-driven one. Cadence’s Rahul Deokar addressed coloring and other 10nm design considerations in his September 17, 2015, talk, “Tackling Coloring, Cell-Pin Access, and Variation at TSMC 10nm,” at TSMC’s Open Integration Platform® (OIP) Ecosystem Forum.
Double and triple patterning are needed at 10nm, the third-generation FinFET process from TSMC. Because of this, “coloring is a must. It’s not an optional task, so the EDA flow is a color-driven implementation,” said Deokar, a product management director at Cadence.
On the physical side, a full coloring flow is required in P&R, extraction, and DRC. Triple coloring may even be used. Other physical considerations include the use of M1/M2 layers for horizontal or vertical routing, which impacts cell architecture and routability, as well as the significant increase in the number of critical rules for the router and placement, Deokar explained to his audience at the Santa Clara Convention Center.
On the electrical side, designers will experience a resistance increase on the metal layers and vias. There will also be variability increases at different metal layers and even within the same layer, along with huge increases in resistance between colors. Other challenges here include the need for a length-based scaling coupling cap, as well as more accuracy in timing and variation, noted Deokar.
Presenting a way to address 10nm design challenges, Deokar discussed Cadence’s 10nm color-driven full digital flow, as shown in the diagram below:
“At 10nm, awareness for color is moving upstream,” said Deokar. “In the past, only the routing part of the system needed to be (color) aware, but now even the placement stage needs to be (color) aware.”
What’s more, noted Deokar, as we move down the design flow, optimization and routing need to be aware of odd-cycle conflicts, when colors at the edges can create ripple effects. The Innovus Implementation System applies preventive steps, and its massively parallel architecture can handle the explosion in design rules to deliver fast turnaround times, he said.
In Cadence’s digital flow, one coloring engine is integrated with several tools. The technology allows a correct-by-construction methodology and supports fixed colors or color variants. Odd-cycle checking and fixing are performed using the coloring concept, which makes debug easier.
With this flow, users can gain 10-20% better power, performance, and area (PPA), up to 10X gains in turnaround time and capacity, full-flow correlation for faster design convergence, and early signoff optimization for reduced iterations.
While discussing how the Cadence flow can result in optimal PPA, Deokar highlighted the new Genus Synthesis Solution, with its globally focused datapath architecture selection capability. Once the architecture is defined and the synthesis optimization has been performed, then the Innovus Implementation System can be used for block-level PPA optimization. And for fast path-based PPA analysis and ECO, there’s the Tempus Timing Signoff Solution.
Deokar noted that since the 10nm layer stack features increasing resistance on the Mx layers, a digital flow for this process needs to be able to take advantage of lower resistance layers. “Using our solution, you have much better timing and density using the layer-aware optimization we have in the flow,” he said.
Concluding his talk, Deokar said, “Through our approach of having early signoff optimization, we’re seeing reduced iterations in the flow and a single-pass journey to the best PPA for your designs.”