Get email delivery of the Cadence blog featured here
SANTA CLARA, Calif.—Modeling power properly can make or break a product’s success, but with today’s electronic systems, that’s easier said than done.
There appears to be no system-level modeling “Holy Grail” in sight; however, progress is being made in aspects of the overall challenge, according to a panel of experts convened here at DesignCon 2015 (Jan. 29).
Aaron Grenat, a Fellow with AMD, put it simply:
“Pieces of it can be solved. It's hard for me to ever see it all solved,” he said. Still, power modeling is so crucial, “I got two guys who do modeling full time. If they get hit by a beer truck on the way to lunch, man we're in bad shape," he added.
Steven Schulz, president of the industry design group Silicon Integration Initiative (Si2), who moderated the panel, laid out the context: Functionality and transistor counts are increasing as are time-to-market pressures.
“Now we have to have earlier visibility and more reliable and early estimation of how energy and power are being consumed as we go through further stages of design,” he said.
Ruggero Castagnetti, a distinguished engineer with Avago, said the goal of power modeling is to start with assessments and exploration at the architectural level and push down through RTL to netlist and layout with feedback, model handshakes, and refinements along the way.
“The whole idea is, the earlier you start the more opportunity you have to not screw up the design. On the other hand, the further down in the flow, the more accurate your results will be.”
But the power problem is shifting from classic leakage issues to dynamic power management issues, which are difficult to eliminate during gate-level design implementation, he noted. In addition, he said there are myriad challenges that need to be considered on the road to solving the problem. Chief among them:
Rajiv Narayan, principle engineer with Qualcomm, said his company uses virtual platforms—basically a simulation of an entire SoC using transaction-level modeling techniques. They run real-world applications on these, analyze results and KPIs. After they get silicon back, they calibrate readings and update models for next-generation product designs.
But he sees three main system-level modeling challenges:
Cadence’s Frank Schirrmeister, group director for product marketing (pictured, left), framed a system-design challenge that’s timely; namely, how is the system software affecting system power? In some cases, he noted, design teams are finding their software benchmarks blown up when an application processor throttles down from, say, 2GHz to 1.5GHz to manage thermal spiking.
The need to “shift left” early in the design to get an early view of such system power considerations is crucial. This is something for which deep cycles of emulation can offer insight, Schirrmeister said.
“At the end of the day it is a performance issue, and that's going to affect the sell-ability of the chip,” he told the audience. “So power, performance, and thermal being connected becomes really important.”
He added that he sees four main needs:
It was during the Q&A that an intriguing concern emerged, proposed in part by Schirrmeister: Is power today enough of a problem (next to increased performance and cost considerations) to really drive big changes in system-level power modeling?
Narayan said an effective system design needs to be attacked holistically.
“For some form factors, the thermal can be the most important,” he said. “You don't want to carry a BBQ in your pocket.”
Grenat offered: “On the flip side, you can have great power but if the performance isn't good enough--the performance per watt per dollars--you could give your chip away and you won't win."
—DesignCon 2015 Panel: Why System-Level IP Modeling Is Difficult
— DesignCon 2015: Tackling PCB Design Issues with New Sigrity Technology (video)
—DesignCon 2015: How a Problem-Plagued Networking Project Gave Birth to Electrical Engineering