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As use of advanced node technologies (FinFET specifically) ramp, more designers are confronting challenges in technology, productivity, and time to market. To get a sense for what engineers need to know about advanced nodes, FinFETs, and parasitic extraction, I sat down with Hitendra Divecha, senior product marketing manager at Cadence, to understand more about where we are today. Q: Hitendra, let's start at a really high level: As we move down into leading-edge nodes—16/14nm FinFETs and beyond—what are the main challenges that designers face today?
A: Well, we can bucket these challenges into two main categories: Increasing complexity and modeling challenges. It’s not just tighter geometries and new design rules, which come with every new process node. We talked about the introduction of FinFET, but there is 3D-IC as well, the number of process corners is exploding, and specifically for FinFET devices, there is an explosion in the parasitics that couples capacitances and resistances. This increases the design complexity and sizes—the netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.
Q: You mentioned modeling challenges and accuracy, what’s happening there?A: Yes, so design complexity is one challenge, but there are various modeling challenges as well. For FinFET devices, for example, there is an introduction of local interconnects, there are second- and third-order manufacturing effects that also need to be modeled. So all of these new features have to be modeled with precise accuracy. Performance and turnaround times are one thing, but if you can’t provide accuracy for these devices, especially as it relates versus the foundry golden data, there is a burden on our customer that they have to over-margin their designs and leave performance on the table.Q: Talk a little more about that. We talk about the enormous percentage of design time taken up by verification in general. How much has extraction, as a subset, grown as we get into these advanced nodes? Can we quantify that?A: Well, from our customers' perspective, while their extraction and time-to-signoff times are increasing, their time to market is shrinking. It can take anywhere from six to eight weeks for designers to close the signoff loop and, as you know, extraction is a critical step in this loop. We have been told by our customers, that while the extraction runtime varies based on the design sizes and types, that full flat extraction at these advanced nodes can take up to three days with their current extraction tools. This puts an enormous amount of pressure on our customers' ability to have design closure in a timely manner to meet their time-to-market pressures. Q: OK, so extraction is a huge pain point for our customers…A: Yes, so huge that we have solve our customers' problems and help them accelerate signoff extraction turnaround time. There’s no way around it. The market has lacked tools that deliver the performance required to produce a significant speed-up in both digital and transistor signoff extraction flows.Q: We’re going to get to that in a second, but before we do, engineers coming around the corner and confronting advanced nodes may not have a sense for what they’re in for. A: Absolutely. Let me put a finer point on that. Signoff extraction has become challenging due to a number of reasons.First, the number of interconnect corners on both the digital and custom/analog sides has exploded partly due to the introduction of double-patterning technology (DPT), first introduced at 20nm and carried over to 16/14nm FinFETs.Second, design sizes are increasing. At 20nm and below, there are more than 70 million net designs. With more corners and larger design sizes, extraction goes from taking a day to a few days to complete. Q: We've talked about complexity challenges...let's move on to modeling challenges.A: Are you ready for this? There are 155X more resistances for FinFET than 28nm devices. This growth means bigger netlists, which impact post-layout simulation performance and require faster simulation runtime. Tools need to model three different resistance types: contact resistance, spreading resistance, and extension resistance. And consider this—the thickness of the 3D gate introduces new capacitances. From FinFET to fringe capacitances, double patterning, and more, the modeling features have just grown more complex, and that stretches out extraction runtime.Q: Parasitic extraction has been a big issue for some time. So what’s wrong with existing flows and tools? A: In some cases nothing, especially for certain designs and older nodes. But as I’ve said, advanced nodes are a different ballgame. In most cases, different extraction engines are used in implementation and signoff, resulting in poorly correlated results that have a negative impact on design closure. Consistent extraction engines throughout the flow—meaning implementation and signoff—is a linchpin to our customers' time to signoff by reducing the number of ECO loops they have to go through.Q: We touched a bit on productivity. So, at 16/14nm and FinFET technology, older extraction technologies can’t necessarily keep up with all the additional complexity you’ve alluded to, correct? A: Yes, parasitic extraction is a means to an end in both digital- and transistor-level extraction flows. However, it is a very BIG means to an end. We listened to our customers' time-to-market challenges, and we’ve brought the massively parallel architecture to bear on the problem. The Quantus™ QRC Extraction Solution, which we just announced, offers up to 5X better turnaround time for both single- and multi-corner extraction versus traditional extraction tools in the market today, provides scalability to 100s of CPUs and machines, and delivers best-in-class accuracy for FinFET designs measured against foundry golden. Also, with the Quantus QRC solution, we continue to provide leading functionality for custom/analog designs, including very cool functionality to address automotive application designs and our new random-walk field solver, Quantus FS. For an example of a customer design like I talked about earlier, we can reduce their extraction runtimes in 10 hours or less instead of three days without compromising on accuracy. In summary, with the combination of performance, accuracy, and our tight integration with our implementation tools, the Encounter® Design Implementation System and the Virtuoso® platform, the Quantus QRC solution delivers the fastest path to signoff.Q: You’re a busy man, so thanks for your time, Hitendra!A: No problem!