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The just-announced Innovus Implementation System aims—among other things—to call a truce in the long design tradeoff tug-of-war between optimizing power, performance, and area (PPA) and maintaining or improving turnaround time (TAT).
Indeed the Innovus system, announced March 10 at CDNLive, aims to help design teams optimize both PPA and TAT and improve both in the process.
Anirudh Devgan described the technology in his keynote. Rahul Deokar offered a deep dive in his paper presentation. Paddy Mamtora, Cadence product engineering group director, and Brent McKanna, senior principal design engineer at ARM, talked to engineers about how ARM used the technology when it was developing its Cortex A-72 architecture.
For a more detailed analysis, you can now check out a Cadence whitepaper on Innovus, written by Deokar and Vinay Patwardhan, product management director, with Cadence’s Digital Implementation marketing team. A collection of materials related to the Innovus technology also can be found here.
-- CDNLive Silicon Valley 2015: A "New Era" in Digital Implementation
-- Anirudh Devgan Q&A: What’s Lacking and What’s Needed in Digital IC Implementation
-- Anirudh Devgan at CDNLive 2015 – How Innovus Will Change IC Implementation
-- CDNLive Silicon Valley 2015: A “New Era” in Digital Implementation