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SAN JOSE, Calif.—Thanks to “the most comprehensive” ecosystem in the industry, 16nm designs are ramping nicely, but close behind will be 10nm devices, which will begin emerging just a year from now.
That was the assessment of Dr. Mark Liu, president and co-CEO of TSMC at the company's annual TSMC OIP event here Tuesday (Sept. 30).
Liu and his colleagues sketched a broad picture of the foundry's technology roadmap, engineering and manufacturing challenges, and paths to overcome those challenges.
He also described an approach to Internet of Things designs aimed at delivering cost-effective, ultra low-power designs into automotive, wearables, home automation, and other applications.
Liu, speaking to a ballroom full of electronics executives from around the world, laid out the challenges:
"The speed of the increases in your design complexity is outpacing the advances of the sophistication of your simulation and validation tools. Your NRE must be skyrocketing. First-time pass at first silicon is almost expected by your boss."
In his wide-ranging technology presentation, Liu highlighted the march to 10nm, where the pace of innovation from IP certification and tools validation to manufacturing is happening much faster.
Liu said he expects 10nm customer tapeouts a year from now (second half of 2015) and risk production in the fourth quarter of next year.
"That's six months earlier than the two-year cadence," he said.
At 10 nm, engineers will enjoy designs that are 2.2X denser and 25 percent faster, while consuming 45 percent less power, according to Cliff Hou, TSMC chief technologist, who presented after Liu.
As far as ecosystem preparation, 35 tools in 11 categories have so far been certified using an ARM Cortex-A15 processor. IP validation, including blocks from Cadence, ARM, Analog Bits, and many others has started six months earlier than normal, Liu noted.
"Our goal is to enable customers' product ramp in 2016," Liu said. "To meet this goal we have to get the 10nm design ecosystem ready."
But with the extraordinary gains at 10nm come new challenges.
To more than double density, TSMC is deploying new innovations in double patterning (DP) and self-alignment technologies. It represents the first time TSMC has required designers to do two-color layout, he added.
"We have to make sure the ecosystem develops solutions to help customers easily adopt this technology," Hou said. Working with its partner ecosystem, TSMC has already developed a full color-aware ASIC flow and a full color-aware custom design flow.
While 16nm still seems like a node that’s fresh from the oven, designs at the node are ramping quickly thanks in large part to a savvy bit of reuse: More than 90 percent of TSMC's equipment for the established 20nm node is being reused at 16nm, according to Liu.
"Our established 20nm capacity can quickly support the coming 16nm ramp up," Liu told the audience. "The yield learning on 20nm production will directly benefit 16nm production."
Today, 20nm production has a monthly volume of 60,000 wafers with good defect density. Already, TSMC's 16nm defect learning has reached a similar level, Liu said, adding, "They are less than six months apart.”
He described the ecosystem for 16nm as “the most comprehensive" in the industry, with 40 EDA tools certified using the ARM Cortex-A15 processor as the validation vehicle and with 700 pieces of IP with functional silicon results covering foundational libraries, LP-DDR4, SerDes, USB 3, and many others.
TSMC plans more than 10, 16nm tapeouts this year and 45 for 2015, including baseband, applications processors, graphics, and cloud networking.
Two weeks ago, the company produced the world's first 16nm FinFET network processor for HiSilicon Technologies Co. Ltd., containing two 16nm core function chips and one 28nm I/O chip integrated using Chip on Wafer on Substrate (CoWoS) technology.
For IoT, Liu said his company is working with partners on IoT-dedicated tools and flows for five key technologies--sensors, processors, wireless connectivity, power management ICs, and advanced packaging--all with ultra low -power features.
"Ultra low-power capability will become a must," he said.
Much of this will leverage CoWoS and other advanced packaging technologies to bring heterogeneous and homogenous devices together in an integrated fashion, he added.
Hou described three offerings for IoT: CoWoS for high-bandwidth, high-speed designs; InFO (Integrated Fan Out) for middle end-of-line, and wafer-level chip-scale package for sensor-logic integrations and cost-sensitive designs.
-- Cadence Tools, IP Enable First Production TSMC 16nm FinFET System on Chip