Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Several years ago, there was a lot of publicity about statistical timing analysis, which was thought by some to be the “next big thing” in IC design. Then things got quiet. But as process nodes head into the 45 nm and below territory, statistical static timing analysis (SSTA) may once again become an important new technology.
Rather than focusing on best-case and worst-case corners and reporting absolute numbers, SSTA returns statistical distributions. In an interview I did in 2007 for SCDsource.com, IBM SSTA guru Chandu Visweswariah cited these reasons for using statistical timing:
But doubts and questions surfaced about SSTA, some of which were captured in an International Symposium on Physical Design (ISPD) debate I wrote about for EE Times in 2007. Skeptics suggested that “intelligent corner selection” might provide an alternative to statistical timing. Others have said that SSTA is really useful only for random variations, and that modeling is a better approach to systematic variations. Finally, the lack of statistical models from foundries pretty much confined SSTA to IDMs until recently.
Still, EDA vendor support grew, albeit without a lot of fanfare. Cadence brought statistical timing into Encounter in 2007, and today the Encounter Digital Implementation (EDI) system and Encounter Timing System (ETS) provide statistical timing analysis and optimization, along with generation of statistical libraries in the statistical ECSM format. To get a handle on what’s happening with SSTA these days, I talked to Mike Jacobs, senior product marketing manager for ETS, library characterization, and ECSM.
Mike said that adoption of statistical timing is just beginning, and has been slower than some people initially hoped. He noted, however, that “there’s a ton of interest every time we talk about it. People ask a lot of questions. They’re just waiting for someone to come out and say, ‘hey, this is here now.’”
One reason it might be “here” now is that foundries are beginning to support statistical models. TSMC, for instance, supports SSTA in its reference flow 8.0. Another is the growing impact of process variations at 45 nm and below. As Paul McLellan noted in a recent EDA Graffiti blog about statistical timing and process variations, “manufacturing is a statistical process and isn’t pass/fail at all.”
While there’s some interest in SSTA at 65 nm, Mike said, most people are looking to 32 nm as the node at which statistical timing will become mandatory. At 45 nm, according to analyst Gary Smith, it’s being used more selectively. “Instead of coming into widespread use at 45 nm, as we expected, it [SSTA] is being used in just the most critical applications,” Gary said. “Just as we ran Spice on our critical paths fifteen years ago, we are using statistical timing on our critical blocks today.”
One major use for SSTA is determining how well a design will yield in silicon. It may show that a given design is “good enough,” saving an expensive rework effort. Mike related how one customer had an ECO that affected the netlist, and was concerned about the impact on negative slack. By running SSTA, the customer was able to determine that the impact would not result in unacceptable yields.
What about the learning curve? “If you can get your head wrapped around the probability of a violation versus a discrete negative slack value, that’s all you really need to do,” Mike said. “Running the tool is really very simple. It’s just like static timing, except the reports are a little different.”
The real challenge behind SSTA is the paradigm shift it involves. IC designers, like quantum physicists, must learn to think in terms of probabilities. Albert Einstein reportedly said, “God does not play dice.” Perhaps – but deep submicron silicon on a foundry assembly line does.
I think your comment “Still, EDA vendor support (for SSTA) grew, albeit without a lot of fanfare…” might be one of the reasons that SSTA has not yet caught on.
At Altos we have produced a number of articles, commentaries, opinion pieces and press releases around the creation of statistical libraries yet the major EDA vendors that form the next vital link in the SSTA design change have remained almost mute. While designers are rightly skeptical when technology is over-hyped, they get darn-right scared off if there is no hype at all! Why haven’t the big EDA vendors who support SSTA been more vocal about this capability?
Two of the world’s largest foundries TSMC and IBM support it and often promote it. A recent study by STARC presented at the EDSfair in Yokohama this past January showed a 29% reduction in TAT, 8% reduction in area and a 23% reduction in leakage when performing timing closure on a block using SSTA over STA.
Numbers like that suggest that SSTA is the next best thing for EDA. What other combination of methodology and tools can make you more productive, reduce your cost, improve your yield and increase battery life! The best part is that the SSTA flow is the same as the STA flow, the only difference being you use a Statistical Timing library and you get an extra number (sigma) in your timing reports!
Jim McCanny, CEO, Altos Design Automation, Inc.