Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
3D integration is a promising new technology that can potentially save space and power by stacking die in 3 dimensions. I recently spoke with Riko Radojcic, Qualcomm design lead for TSS (Through Silicon Stacking – Qualcomm’s term for 3D ICs), about how Qualcomm is deploying this technology and developing a design environment that can support it. Radojcic was on his way to Nice, France, where he’s presenting a talk on 3D integration and through-silicon vias (TSVs) at an April 24 workshop at the DATE Conference.
Why is Qualcomm interested in this technology? Radojcic said TSS can provide form factors that save board space and power. TSS can also support heterogenous integration with its ability to place digital logic, analog, RF, and memory on different die. As for cost, he noted that TSS is a new technology that is not going to compete with wire bond right way. But the costs may be justified. “If we can save a lot of power, then it may be okay if it costs us a few pennies more,” he commented.
Qualcomm is currently developing its first implementation of what it calls a “stage one” class of TSS products. These consist of a functionally partitioned two-die stack. Combinations could include analog and logic, RF and logic, or memory and logic. In future stages, Radojcic said, Qualcomm expects to design with multiple tiers and more than two die.
Radojcic said that Qualcomm describes the design approach for stage 1 as “2.5D” rather than “3D.” As such, tools need to understand that a die has two sides, but do not need to cope with multiple die. As a result, “we do not need disruptive changes to the design flow,” Radojcic said. But further down the 3D roadmap things change. “If you want to build a 3-die stack or a logic-to-logic stack where you partition across tiers, then synthesis, place and route, and design for test all need significant upgrades.”
Qualcomm uses TSVs for inter-die interconnection. TSVs provide far more density than any other technology, Radojcic said. Currently, Qualcomm is using thousands of TSVs, but future products may have tens of thousands or even hundreds of thousands. But TSVs raise a number of challenges. “They require thinning of the die, which is a large source of concern for us,” he said. “This raises mechanical and thermal concerns.”
TSVs also raise design challenges. Where do you place the TSVs, and how do they impact the rest of the design? To enable 3D design with TSVs, Qualcomm is working with its partners to develop a flow that consists of three methodologies:
Test is another looming issue. “So long as partitioning is done along functional lines, it’s not big,” Radojcic said. “But when you start partitioning logic across tiers, the test challenge becomes significant.”
TSS will require IC/package co-design. It will require rules or models that make chip designers aware of constraints. “The beauty of TSS is that it blurs the lines between packaging and silicon design,” Radojcic said. “TSS, by definition, is the integration of these.”
Collaborative partnerships are a crucial part of Qualcomm’s work on 3D ICs. For example, Qualcomm is working with Cadence on thermal solutions, and Radojcic said the Cadence collaboration and Qualcomm’s use of the Encounter Digital Implementation System helped Qualcomm produce its first TSS test silicon.
Qualcomm’s staged, collaborative approach to 3D IC design appears to be paying off. “We are developing products for our first implementaiton,” Radojcic said. “We are working with a number of key partners in our supply chain.”
Well, the 3D IC technology is gaining momentum. I wonder how much it will take for this technology to become a standard in consumer electronics (I mean, TSV-based electronics).