Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
EDA software, embedded software, and physical chips can all fall victim to piracy and misuse. How can this be prevented? Cadence architect Scott Baeder, chair of the EDA Consortium Anti-Piracy Committee, is organizing a July 28 panel at the Design Automation Conference (DAC 2009) that will present two different approaches to the problem.
Scott’s work with EDAC focuses on EDA software, but the DAC panel will take a broader view. One panelist is Bill Lattin from Certicom, a company that provides software that allows critical functionality of a chip to be disabled until the semiconductor company turns it on. (Certicom also developed the elliptic cryptography algorithm used by FlexLM, a license manager employed by many EDA tools). Another panelist is Vic DeMarines from V.i. Labs, whose CodeArmor Intelligence product detects piracy, gathers evidence of infringement, and identifies users of pirated software.
These two panelists represent two different approaches to protecting intellectual property, applicable whether that IP is an EDA tool, embedded software, or a physical chip. The first approach involves “hardening” IP so that it’s more difficult to steal or inadvertently misuse. For example, an EDA tool may be hardened with the security provisions of the FlexLM license manager, and a chip can be hardened with Certicom software that doesn’t let the chip operate if somebody steals a wafer.
The second approach is a bit more delicate. Here, users of unauthorized IP are identified and approached. In some cases, individuals within companies use unlicensed software without their company’s knowledge, or companies inadvertently use licenses improperly. In others, companies know they’re using stolen IP. The point is to convert those companies to fully paying customers – or take action to shut them down, if that doesn’t work.
As described in a recent webinar hosted by Scott Baeder and Vic DeMarines, EDA software piracy has become a serious problem. You would think that expensive, complex IC design software that requires a high level of support wouldn’t have a big piracy problem. That is generally true. But there is also a lot of low-cost, mainstream EDA software available on PCs for tasks such as PCB design, FPGA design, and analog/RF design. And that’s where the problem lies.
Scott said that perhaps 30 to 40 percent of PC-based EDA software is “unpaid for.” He noted that cracked versions of PC-based EDA software releases are often available via BitTorrent, a peer-to-peer file sharing protocol, within two weeks of the release. EDAC does not yet have “good actionable data” on piracy of Linux-based EDA tools, however.
As a design capability becomes more mainstream, odds of misuse and piracy grow larger, Scott said. He’s concerned that 130 nm chip design is becoming sufficiently “run of the mill” to possibly attract piracy. On the other hand, he noted, software piracy is starting to decrease in countries such as China, Russia and India “as both the governments and the culture are realizing that there are intellectual rights and value associated with it, and that using software you don’t pay for is theft.”
One must be careful to separate outright piracy from accidental misuse. For example, a design team might accidentally use a host ID more than once and run more software than a license agreement allows. EDA vendors are thus focusing on making it harder to make such a mistake. “We are going to a lot of effort to make sure there’s got to be overt action to steal software,” Scott said.
Scott hopes DAC panel attendees will come away with a better understanding of the piracy problem and anti-piracy techniques. The panel will take place 10:30 – 11:15 a.m. Tuesday, July 28, in the DAC Pavilion at booth #1928. A short video describing the panel is available at the EDAC web site.