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You would think that designers would not welcome restrictions on what they do, but panelists at the recent Design Automation Conference saw restricted design rules (RDRs) as a helpful and necessary step towards 32 nm/28 nm IC design. Panelists from AMD, TSMC, Texas Instruments, and Cadence spoke Monday, July 27, at a panel on advanced node design at the Cadence Ecosystem booth.
This was the first of five panels held at the booth, all of which included three customer or partner representatives and one Cadence representative. The panels focused on user challenges and experiences. I moderated four of the panels, including the advanced node panel.
One overall message was that the design and modeling infrastructure for 32/28 nm is ready, although full volume production is still a ways off. Tom Quan, senior director of EDA and design service marketing at TSMC, started the panel with a look at TSMC’s 28 nm design infrastructure. It includes statistical Spice models, a unified DFM framework, a reference flow, and RDR-based standard cells with regular layout patterns.
“We will definitely see the use of RDRs to meet performance targets and reduce variability,” said Arjun Rajagopal, member of technical staff at TI’s DSP group. According to a chart he showed, RDRs will take up some extra area, but will help reduce variability and provide benefits when it comes to reuse, predictability, simplicity, manufacturability, and resolution enhancement techniques (RET).
Norma Rodriguez, senior member of technical staff at AMD, spoke in some detail about the benefits of using RDRs at 22 nm and below. Design rule complexity is unmanageable beyond 32 nm, she said, and design intent is getting more complicated. As such, there’s a need to adopt regular layout patterns and limit the number of design configurations. “What we’re calling RDRs will allow us to build very complicated designs,” she said. “If we follow RDRs, lithography will be a lot easier, and we’ll have better variability control.”
Norma Rodriguez, Tom Quan, Arjun Rajagopal, and Nitin Deo (left to right) participatein the advanced nodes panel.
In the Q&A period, I asked how restrictive the “restrictive” design rules are going to be at 32/28 nm, and what the tradeoffs are in terms of area, performance and power. Quan said TSMC will have a standard cell library version with one-directional pitches. Designers will give up some area but will save power, have better control over leakage, and have much better reliability than they would with random layout patterns, he said.
Rodriguez said that AMD will identify “forbidden pitches” and tell designers which pitches they can use. “In reality this helps you,” she said. “It makes layout people and designers more efficient, and they have more time to use in different ways.”
Nitin Deo, group marketing director at Cadence, noted that there’s a “marketing problem” with the RDR terminology. “RDRs should be called MDRs – manufacturable design rules,” he said, “because what you do is use such a regular layout that automatically the design becomes more manufacturable.”
Panelists also raised the following points:
The good news, as reported by Nitin Deo:
“We are ready with the infrastructure that is required for supporting 32 and 28 nm. We’ve done several designs and we’re tracking about 30 different projects with partners. So far as the tool infrastructure is concerned, it is absolutely ready, whether it be manufacturing models, or rules, or the independent analyses that are required.”