Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Norma Rodriguez, senior member of technical staff at AMD, has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted layout patterns as well as DFM tools.
At the recent Design Automation Conference (DAC), Rodriguez gave a presentation at the Cadence Ecosystem booth about a capability called DRC Plus. It augments standard design-rule checking by using fast 2D pattern matching to identify hotspots, or layout patterns that result in poor printability. Embedding this capability into a router lets designers identify and fix potential 2D yield detractors. AMD, Global Foundries, and Cadence contributed to the project.
Rodriguez was also a panelist at the advanced node panel at the Ecosystem booth, where she talked about restricted design rules (RDRs) and DFM. In a subsequent interview, I asked Rodriguez what problems got worse at 32 nm compared to 45 nm.
“What is new is that all the metals came with a very problematic litho situation, so there were a lot of forbidden pitches we needed to take care of,” she said. Further, dual stress liner (DSL) technology gets more complicated at 32 nm, and it’s difficult to model the correlation between performance and stress until large production volumes are available.
In the attached video clip, Rodriguez talks about how 32 nm is a “middle point” between 45 nm and 22 nm with respect to RDRs, and what “truly restricted” design rules at 22 nm will involve. She also addresses a question about area tradeoffs resulting from RDRs.
If video fails to launch click here.
RDRs may reduce the need to run model-based DFM tools, Rodriquez said, but they won’t eliminate it. Model-based DFM will still be used for verification, but with RDRs, models will be less crucial for design.
Rodriguez noted that there are typically two “DFM insertions” into the design flow – one that retargets designs for mask data preparation, and another that brings in yield recommended rules (YRCs) to improve manufacturability. A better approach for 32 nm, she said, would “combine retargeting and YRC all in one step and do the DFM as you do your construction.” This, combined with regular patterns provided by RDRs, will help create designs that are “very OPC friendly and manufacturing friendly.”
Who on the IC design team needs to be concerned about manufacturability? Is it just the layout people, or also the logic designers? Her short answer: “Everybody.”
Rodriguez’ advice for design teams considering 32 nm is “to not be scared, but to embrace the idea that things are to the point where we need to collaborate together. Design rules the way we used to think of them are not sufficient. That’s a fact of life you have to live with. You have to check for patterns, you have to check for different types of litho rules to do your design, and you have to favor uniformity.”