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Steve Carlson is vice president of marketing for low power and mixed-signal solutions at Cadence. In this interview, he discusses the increasing importance of mixed-signal SoCs, describes key challenges, and outlines Cadence strategy and solutions.
Q: The term "mixed signal" has been around for a long time. How does Cadence define it?
A: Any design that contains both digital and analog content can be considered a mixed-signal design. From small to enormously large, from nearly pure analog to predominantly digital, we categorize designs as mixed signal. As such, it is getting tougher and tougher to find designs that are not mixed signal.
Some people assume that “mixed-signal” designs are mostly analog or RF, and consider mostly digital designs with some analog circuitry to be “digital.” This is a distinction that we don’t agree with. As we see more and more analog IP blocks integrated into SoCs, we need to recognize that these SoCs possess all of the same challenges as any mixed-signal design, while being interwoven with all of the “digital” challenges of verification, low power, and complex timing closure at advanced nodes.
Q: Why is mixed-signal SoC design an important area to address?
A: Our customers are reaching the critical pain threshold in digital design methodologies where a hard and fast, divide-and-conquer, “treat the analog like a black box” design flow is starting to break down. The number of analog IP blocks grows with every SoC generation, and that creates a corresponding likelihood that cross-domain boundary issues will arise and create scheduling problems or chip failures. Industry figures tell us that over 50 percent of respins are caused by mixed-signal issues, and that 50 percent of the design effort may focus on 10 percent of the transistors.
Customers are facing challenges in their design flows that require a much tighter coupling of analog and digital design environments and teams. This fact puts Cadence in the lead position to address SoC design team needs. Cadence possesses a unique, historic, leading position in all things analog, custom and RF, and a long lineage of supporting the evolving requirements of mixed-signal design teams. The analog and digital SoC trend creates the opportunity to combine our digital verification methodologies and highly competitive digital design, test and implementation technologies with our proven analog solution. The OpenAccess database lets us achieve transparency in the design process between design domains.
Q: What is the scope of Cadence’s mixed-signal solution?
A: Cadence has all of the necessary components for a comprehensive analog and digital design solution. Clearly the Virtuoso platform creates the foundational technology, experience, ecosystem and customer base. The OpenAccess-based links between Virtuoso and the invigorated Encounter Digital Implementation system create transparency across the design domains. Differentiated design planning and prototyping capabilities complement the cross domain sign-off technologies in the Cadence solution.
Working from a common underlying representation ensures that the analog-centric and digital-centric design views are always accurate, and that the interrelationships for analysis and verification are considered. Through the use of constraints, designers can capture design intent at the front end and ensure that it is fully implemented through physical design. This may require more designer effort up front in the initial design process, but it allows more sophisticated IP design reuse and automation through the rest of the design process.
The mixed signal simulation capabilities of the Virtuoso and Incisive platforms, coupled with a metrics-driven verification methodology, provide the capabilities necessary to ensure proper functional behavior. Keeping up with new challenges, such as simulation of power shutoff of analog IP blocks in an SoC, has been a key focus in keeping up with the evolving needs of the marketplace. To provide a full array of choices and capabilities, we support a complete set of modeling abstractions, including new options for real value modeling that allow fast execution in chip-level verification.
The Allegro platform, like Virtuoso, has been bringing analog and digital together for a long time. Allegro supports the trend towards multi-chip and stacked die packaging solutions. Finally, the gradual migration towards higher levels of abstraction and system-level design also play to the strengths of the company in chip planning and system design and verification.
Q: Verification is a big challenge in analog and digital design. Why, and what are customers most concerned about?
A: For most designs today, verification is the biggest cost. Mixed-signal designs are no exception. Customers are seeing, simultaneously, the growth in verification cost and the increasing complexity of domain interactions as more analog IPs are integrated into SoCs. It’s getting more difficult to complete full-chip simulations. New classes of failures are occurring, while old causes are being exacerbated.
Modeling, testbench development, and functional coverage increase the complexity of mixed-signal verification. Mapping digital concepts to the world of analog/RF is challenging, but is needed to help improve designer productivity. Managing runtime versus accuracy is critical, especially when considering system validation. The use of characterized models is essential to this balance. When taping out a design, designers need to have confidence that they have accounted for parasitics and noise in their final simulations.
Q: What tools or methodologies can ease the mixed-signal verification burden?
A: There are two parts to verification -- making sure you have specified the intent correctly, and ensuring that intent is retained through the implementation process. The first part is where simulation and advanced verification methodologies come into play. Applying the discipline of a metrics-driven verification methdology enables design teams to have very specific goals and strategies for the measurement of verification progress. Bolstered by technologies for testbench automation and multi-abstraction level modeling solutions, verification teams can craft strategies that eliminate risk and improve the predictability of the schedule time required to reach a specified verification quality level.
The second part, ensuring the original intent is retained during implementation, calls for a hybrid of static and dynamic technologies. Formal equivalence checking for digital circuitry has been in use for a long time now. Unfortunately, for analog design, there is no complementary static technique available today. So, simulation must be employed. The interfaces between analog and digital circuitry do, however, provide the opportunity for further static checking.
Proper design partitioning can significantly reduce the verification burden. Modeling with wreal can enable more behavioral level modeling, which can reduce lengthy runtimes while maintaining a high level of accuracy. Top-down floorplanning can reduce the parasitic impact of top-level interconnect. Applying the Common Power Format (CPF), static timing analysis, and constraints to the design make it possible to do more checking during physical implementation and reduce the need for simulation.
Q: How does low-power design for digital and/or analog IP impact mixed-signal SoCs? What are the implications for verification?
A: Low-power design impacts virtually every aspect of the design starting with its architecture. Exploring design trade-offs requires significant verification and can often impact how a block will get implemented. The ability to capture designer intent with CPF enables not only early exploration, but insures the front-end intent is implemented and verified in the back-end. The Virtuoso AMS Designer simulator can leverage CPF to understand the consequences of power shutoff in mixed-signal designs.
Q: What are the primary challenges in mixed-signal physical implementation? What are the solutions?
A: Mixed-signal implementation requires a detailed knowledge of the physical constraints and and assumptions that were made while designing block-level IP. Substrate and coupling noise can degrade performance, limit yield, or worse yet require another design pass. Avoiding these issues requires constraint-driven physical design that can capture and verify both physical and electrical constraints.
Automating physical implementation with captured constraints provides a much needed boost to productivity. Since RF/analog and digital designers have classically worked in separate cockpits, enabling them to be productive in their own environments with common data and constraints is critical for their success.
Many designers don’t want to start a floorplan before the IP is well defined, for fear it will radically change the floorplan. But if they wait, they consume precious time-to-market. Cadence endorses a flow that allows concurrent top-level floorplanning and IP design, and uses OpenAccess to make it easier to update IP sizes and pin locations.
Q: What can be done to foster greater cooperation and collaboration between analog and digital design teams?
A: Simplifying how models are created, how constraints are captured, and how data is analyzed and verified enables tighter collaboration between design teams. Enabling flexible design flows that can support both analog-centric and digital-centric designers at more stages of the design process will help minimize schedule risk and improve the probability of first time silicon success.
Q: What can you say about Cadence’s R&D investment in mixed-signal design?
A: Cadence’s R&D investment continues to be the largest in the industry. That investment includes a rich vision for mixed signal-design. Having far and away the largest user base for mixed signal design, Cadence has a roadmap that spans the technology portfolio and has a close connection to solving customer challenges.
So, without divulging too much of the proprietary roadmap, we can say that a huge amount is happening to complement to industry’s only complete mixed signal design solution.
Note: Cadence will hold a full-day Mixed-Signal Design Summit Oct. 27, 2009 at Cadence headquarters in San Jose, Calif. At the Summit, customers will discuss the challenges of mixed-signal design methodologies and present solutions. Product demonstrations will be offered and Cadence R&D experts will be available. For further details, see https://www.cadence.com/cadence/events/Pages/event.aspx?eventid=260.