Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Stan Krolikoski, group director for standards and ecosystems at Cadence, has been elected chair of the IEEE Design Automation Standards Committee (DASC), which oversees all EDA-related IEEE standards activities. In this interview he discusses the role of the DASC, identifies key 2010 EDA standards, and comments on how well the EDA standardization process is working.
Q: Stan, congratulations on your election. What exactly does the DASC do?
A: The DASC is the sponsor for all EDA standards that come out of the IEEE. Working groups for SystemVerilog, VHDL, e, SystemC, and IP-XACT all come under the DASC. The DASC chair approves the PAR [project authorization request] that defines the scope of a standard, and forwards it to higher levels of the IEEE for further approval.
One of the major functions of the DASC is to make sure that standards groups are compliant with IEEE rules. To keep within the timelines, a standard has to be updated or at least re-affirmed every five years. If there are any concerns that the rules aren’t being followed, the DASC will moderate the dispute. The DASC also works with the governing committees of the IEEE and represents the interests of the working groups in these higher-level committees.
Q: Who is on the DASC? Who are the other officers?
A: There are about 80 individuals. Probably about 60 percent are representatives of user companies, and 40 percent are representatives of vendor companies. If you look at the membership list you’ll see that many of the top semiconductor companies have members there. The highest concentration of members is in Europe and the U.S.
As for officers, Karen Bartleson [Synopsys] will be the vice chair, Kathy Werner of Freescale is the secretary, and we have an open position for treasurer that I will appoint.
Q: How has the IEEE standardization process evolved in recent years?
A: At this point, I think the IP policy has been fixed. Non-discriminatory licenses for patents are required. The IP policy was hammered out with user and vendor companies – it wasn’t imposed from above.
The IEEE has pretty much gone to an entity-based committee structure. It used to be that if company X had 20 members on the committee, they had 20 votes. Now it’s essentially one company, one vote. I think that works pretty well in that you don’t have anybody packing the jury, so to speak. The other thing that’s working well is that we have feeder organizations like Accellera, OSCI [Open SystemC Initiative] and SPIRIT that donate work to the IEEE. The IEEE doesn’t rubber-stamp anything, but at least there’s something concrete to work off of.
Q: What are your priorities as DASC chair?
A: We need to internationalize the group a little more. It’s very heavily concentrated in North America and Europe. We have Asian members, but the meetings happen at 8 am in the morning California time, when it’s the middle of the night in Asia. One thing I’ve proposed for the DASC, and other IEEE meetings, is rotating the times. For example, we could have a meeting at 5 pm California time, which is morning in Japan.
Otherwise, we just want to make sure that any standards we have are supported and are being actively worked on, and are not just out there as a number.
Q: What IEEE EDA standards will most stand out in 2010?
A: One that will be important is SystemC [IEEE 1666], a group I happen to be chairing. We had a 2005 standard, but since 2005 there has been a lot of work in transaction-level modeling within OSCI, and now it’s time to make this into an IEEE standard.
There are also a fair number of standards that will be coming onto the scene in 2010, even if they were approved in 2009. For example, SystemVerilog has been updated and is coming out now. Others include the IP-XACT standard from SPIRIT, which will now become a full IEEE standard, and Property Specification Language [PSL].
Q: What 2010 standards efforts would you highlight outside the IEEE?
A: There is a lot of interesting work going on in Accellera. The verification IP working group has just come out with an interoperability library that allows VMM [Verification Methodology Manual] users to take OVM [Open Verification Methodology] VIP and integrate it into a VMM environment, and vice versa. There is work on a unified coverage interface standard that should be coming out in 2010.
In OSCI, there’s some good work on the CCI [Configuration, Control and Inspection] standard, which will help people write models so they’re inspectable and debuggable. We also have a SystemC-AMS standard coming out. And some work has been done on a synthesizable [SystemC] subset. As high-level synthesis becomes more prevalent, I think we need that standard.
Q: Cadence is involved in many EDA standards efforts. Why?
A: Let’s put it this way. If there were no standards, if all the IEEE and Accellera and OSCI standards disappeared, most of our tools would disappear, most of our flows would disappear. Cadence from the beginning has been committed to having a well-built standards infrastructure. It provides the basic infrastructure upon which we build our value.
There’s also the fact that any EDA vendor is dominant in some parts of design flows and not dominant in others. Sometimes you want partners, other vendors, or users to be able to plug into your flows. You can’t do that unless you have interoperability, and the only way to have interoperability is to have standards.
Q: Some standards are widely adopted, others are not. What makes the difference?
A: It’s not necessarily a function of the goodness of the technology. It often depends on who’s supporting it. One of the nice things about feeder organizations like Accellera and OSCI is that they have a good mix of vendors and users. Whatever comes out of these organizations and goes to the IEEE typically has the blessing of both the vendor and user communities, so they tend to be adopted.
Q: Is EDA standards development getting easier? Where are the bottlenecks?
A: I think it’s getting easier. First, the feeder organizations have a better base of support. And with Wikis and Webex, the nuts and bolts of completing standards have become easier. We have bug tracking systems and all the things engineering teams have, and we have better IP policies. We’ve all learned about maintaining the integrity of our patents.
But there’s always competitive tension in terms of technology donations and the acceptance of technology. That is always going to be there. And it’s not just Cadence versus Synopsys; there are also rival semiconductor vendors on the same committees. I really think standards wars are exaggerated. Standards organizations are more like peace negotiations where competitors work together. An occasional battle flares up, but there’s more peace than war.
In general, I think the tone of discourse in standards groups has come to the point where most things get done well. Most things get done without contention and what comes out is pretty good.