Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
technologies are of no value unless there's a coherent, workable methodology
that supports them. SystemC transaction-level modeling (TLM) has lacked a
methodology that goes all the way to silicon without major gaps. Independent
verification consultant Brian Bailey filled in some of those gaps at SystemC Day at the
DVCon conference Feb. 22.
Brian spoke at the
first half of SystemC Day, which was the North American SystemC User Group (NASCUG) 12th
meeting. Other morning talks included an overview by Open SystemC Initiative (OSCI) chair Eric Lish and a keynote by
analyst Gary Smith. The second half of SystemC Day included a DVCon tutorial
on the proposed OSCI SystemC synthesis subset, taught by Michael
McNamara of Cadence, Michael
Meredith of Forte, and John Aynsley of Doulos.
As he began his talk,
Brian noted that his presentation is based on consulting work he's recently
done with Cadence. It's a "work in progress," he said, but he outlined some
major characteristics of a TLM-driven design and verification methodology,
including the points below.
Design and verification must work in tandem
traditional "V" shaped flow in which design and verification proceed
separately, and come together only at the end. Verification needs to occur
every time a transformation is made in a model. "We must verify as we make
decisions rather than leaving them until some point much later in the flow,"
Separation of concerns simplifies modeling and verification
computation should be treated as independent concerns. This way, both
communications and computation blocks can be reused without being dependent on
one another. If you take computation blocks and connect them together without
communications, you create a protocol-agnostic virtual platform. "You want a
methodology that allows you to pick any two things and put them together in a
way that doesn't require re-verification," Brian said.
and architecture should be treated separately as well. "We don't want to
pollute our functional description with how we're going to implement it."
Working with multiple abstraction levels
TLM-driven design and
verification will occur in a "multi-abstraction" environment. The best approach
is to start from the top with algorithm design and verification, go through the
loop to complete that process, and move down to architectural verification,
while reusing as much from the algorithmic level as possible. The next step is
to move from architectural to micro-architectural verification, again reusing
as much as possible.
Adapters and interfaces
The design process
will likely start with C/C++ algorithmic models. To move to architectural
models that can be used in virtual platforms, it will be necessary to define
hardware/software boundaries, registers, and concurrency. This is where SystemC
comes in. As model transformations proceed, there will be a need for "adapters,"
which are simple routines that handle such concerns as rate matching and buffer
The flow that Brian
outlined relies heavily on high-level synthesis. Since the OSCI TLM 1.0 and 2.0
standards are not synthesizable, the flow uses an interface based on OSCI TLM
1.0 that does not strictly adhere to the standard. For example, it leaves out
simulation features that are not synthesizable, and adds missing features
needed for synthesis such as reset. It also brings in "generic payload"
capabilities from OSCI TLM 2.0. (A blog
I wrote last year talks more about TLM 1.0 versus 2.0).
What about third-party TLM IP?
Actually, this wasn't
part of Brian's presentation, although in response to a question he said that
defining a synthesizable SystemC subset will help enable the IP industry. It
seems to me that the availability of TLM IP is the next big question, but
that's a topic for another blog.
the NASCUG meeting will be available at the NASCUG
web site. Meanwhile, for a Cadence perspective on SystemC, see the video
interview with Steve Svoboda in the SystemC
Day blog by Joe Hupcey III.