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It's hard to believe that the Design
Automation Conference is less than one month away. It is even harder to
believe that this will be my 26th DAC. As always, there is way too
much happening at once at DAC. Here, I've put together a "short list" of items
on the DAC conference
program that I think look interesting.
This blog posting does not include breakfasts, lunches,
dinners, parties, meetings, and other special events not on the DAC conference
program. Some of the events listed here have Cadence involvement or
sponsorship, but this is by no means a complete list of Cadence activity at
DAC. For that, see our newly launched DAC microsite. The
47th DAC (hard to believe that, too!) runs June 13-18 in Anaheim, California.
Standard disclaimer: Event details are subject to change.
Sunday June 13
The EDA Consortium and the DAC Executive Committee will get
things going with a Kick-Off
Reception Sunday at 6:00 pm. What's unique and different this year is that
sponsorship comes from user companies, including ARM, Intel, NVidia, Qualcomm,
and STMicroelectronics. The preliminary agenda mentions just a couple of short
Monday June 14
Monday is a good day for getting out on the exhibit floor. The
Pavilion Panel with analyst Gary Smith
(really a one person presentation) on "What's Hot at DAC" is an annual
As I noted in a recent
blog, a free Monday Advances
in Process Design Kits Workshop will discuss the OpenPDK Coalition recently launched by
the Silicon Integration Initiative (Si2). The workshop runs 1:00 pm to 4:00 pm
and includes presenters from Si2, Intel, TSMC, Cadence, Mentor, and SpringSoft.
Tuesday June 15
The technical program starts as Douglas Grose, CEO of
GlobalFoundries, offers a keynote speech on the move "from contract to
collaboration" and its impact on foundries. Management
Day starts right after this speech and runs Tuesday from 10:30 am to 6:00
pm. Sponsored by Cadence, it's aimed at managers and decision makers. It has
three sessions: Decision Making for Complex SoCs, Tradeoffs and Choices for
Emerging SoCs, and Making Critical Decisions for Emerging SoC Development. I am
moderating the first session, starting at 10:30 am. All presenters are from
The User Track
starts Tuesday and provides a three-day program with over 110 presentations.
This is where you learn how real design teams have solved real design problems.
Wednesday June 16
In a Wednesday keynote speech, Bernard Meyerson, IBM fellow,
growing IT demands and the end of classical semiconductor device scaling.
Some of the most interesting DAC panels occur Wednesday. A
panel on 3D
stacked die starting at 9:00 am is organized by Samta Bansal of Cadence and
Juan Rey of Mentor Graphics. Panelists are from foundries and user companies.
At 2:00 pm a panel entitled "Does IC Design
Have a Future in the Clouds?" will look at the attraction of cloud
computing for EDA and consider some of the perceived obstacles. Organized by
Andreas Kuehlmann, director of Cadence Research Labs, the panel includes
speakers from Cadence, Synopsys, Xuropa, U.C. Berkeley, Altera, and Amazon.
A panel on the future of low-power
design, set for Wednesday at 4:00 pm, includes speakers from Cadence,
Synopsys, Qualcomm, Renesas, and Texas Instruments.
Thursday June 17
There are plenty of reasons to stay over for Thursday. One
Enablement Day, which starts with a session entitled "Enabling Tomorrow's
Complex SoCs." Gadi Singer of Intel is the keynote speaker, and John Bruggeman,
Cadence CMO, is one of the presenters. Session 2 examines "Tradeoffs and
Choices for Embedded Solutions," and session 3 is titled "Leveraging a Diverse
Design Ecosystem for Emerging SoC Development." Companies represented in these
sessions include Cadence, MontaVista, Xilinx, TSMC, ARM, Open Silicon, Mentor
Graphics, Virage Logic, and Altera.
Iqbal Arshad, corporate VP at Motorola, will give a keynote
the Motorola Droid." It will describe "the synthesis of new hardware that
is tightly coupled with a new software experience."
A "joint" DAC and User Track
panel will take place Thursday, with speakers from Intel, IBM, Oracle,
Cisco, and Broadcom. Finally, starting at 4:30 pm, a panel will consider the best input
language for high-level synthesis.
Panelists are from Synfora, Cadence, Bluespec, Forte, Mentor, AutoESL, and Calypto.
The above listings represent a fraction of the events on the
DAC conference program. A complete program listing
can be found on the DAC web site, as can registration information. I
hope to see you at DAC 2010.