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Applied Micro Circuits Corp. (AMCC) is designing some challenging
SoCs for multimedia network applications. In this interview Sumbal Rafiq,
director of engineering at AppliedMicro,
talks about challenges such as cost, manufacturability and complexity, and
discusses how he thinks the EDA360 vision can
Q: Sumbal, what are your responsibilities at
A: I am responsible for VLSI engineering at
AppliedMicro. My group handles three primary functions -- synthesis, timing,
and physical design. The synthesis function includes physical synthesis as well
as formal verification. The timing function includes constraint development and
timing verification. Physical design includes all implementation steps from
synthesized netlists to tapeout to the fab.
In general, our chips are practically all SoCs. We develop
or acquire a lot of IP blocks and integrate them to form complex high-speed
chips for our customers. Internally developed IP blocks include analog,
DSP and high speed processors.
Q: What are your primary challenges in SoC development?
A: I think the main challenge has to do with cost, just like
the EDA360 paper talks about. For a product to be marketable and competitive,
cost is everything. How do we design a chip that will be cost-effective and yet
low power? At the same time, we need to design chips in a
way to generate good yield, and achieve a total low cost target
including a package.
In many cases, the IP sizes that are available are not very
optimized. When we put the IP together, we are trying to design a chip of a
particular size. If we compact the chip too much, we will have to spend lots of
effort in terms of manufacturability. If we expand the chip too much, die size
will be large and cost will be impacted.
In terms of implementation, synthesis is reasonably
simple. If you over-constrain the design while synthesizing, however, you get
an unoptimized netlist. Part of it can be recovered later during place and
route, but even so, margining correctly up front can generate the best
results. If you are trying to have multiple power domains or power shutdown,
synthesis becomes quite difficult. Formal verification also becomes challenging,
especially when you are surgically improving or designing for low power. For
high speed designs or designs with a lot of complex clocks, physical synthesis
is becoming almost a must.
Timing closure with multiple corners and multiple modes is
making the implementation harder. For designs that are sub-40nm, there are generally
over 30 timing closure scenarios. This makes the design implementation cycle
longer and can result in an over-margined or over-designed silicon.
Physical design has a lot of challenges that impact cost.
For example, you can get IP for a particular [metal] stack, and there are three
or four different kinds of stacks. The IP blocks available for each stack are
different. If we make a different variation of the same chip with a different
metal stack, we have to get IP developed for all our stacks.
Q: Is SoC complexity a challenge for you?
A: One thing I noticed in the EDA360 paper is a discussion
about capacity to implement large designs. Previously we had tools from another
vendor that we used to do physical design. Due to capacity limitations we had
to make up 20 plus sub-blocks for a relatively medium-sized chip. Now we have
Cadence [Encounter] and we have blocks with up to four million gate instances
that we implement flat. This used to be the total instance
count of our medium sized chips. Capacity of the tools has enabled
us to integrate 30 million placeable instance designs very
successfully, which is a very positive contribution from the EDA vendors.
Q: What did you find interesting in the EDA360 vision
A: I think the general idea of the paper is pretty good.
It's about taking things at a higher level of abstraction and getting a bigger
picture first. I think the idea has been around for a while, but hasn't been
put on paper in this way.
At AppliedMicro we do a lot of implementations along
similar lines. We try to do tasks concurrently. For example, power is very
important to us and we try to put it into perspective up front. We start
looking at power at the RTL level and we have tools to help us monitor power as
we go along during the course of the projects. Any major jump in the power is
detected even before physical implementation starts, and the RTL code is modified
We also monitor the die size and we see how much of an
improvement we can make. We take the same approach with manufacturability. We
do concurrent optimization and keep all these parameters in mind
while implementing the design - power, area, manufacturing yield. The
concurrent approach is good!
Q: One point made in the EDA360 paper is that more tool
support is needed for IP integration. Do you agree?
A: We do see some issues with integration. Different IP
blocks have different integration issues, and this is true for internally
developed IP as well. The long-term goal as to where the IP will be
used makes a big difference. When you are going from one chip to another,
requirements may change slightly, and you may find yourself designing the IP
A slight overdesign and more planning up front might make IP
more useful so it can go into four or five different applications.
This ultimately affects profitability of the company and the industry as a
Q: The EDA360 paper talks about a "profitability gap."
Has profitability become more of a concern for IP integrators?
A: I think that's very true. At the end of the day, all that
matters is whether you can make the product yield something in terms of profit.
Right now tapeout costs are going past a million and a half [dollars]. If you
can meet the product goal the first time with a solid high yield
silicon, it will reduce much of the overall project development cost.
Q: What's your overall assessment of the EDA360 vision
paper? Anything you'd like to see added?
A: The best thing is that you are looking at a bigger
picture up front instead of starting from the bottom. I really like the idea of
a top-down starting point. It matches my thought process. If you have a broader
vision and plan ahead, you can reduce a lot of features in the chip that
increase the overall cost of the design.
There are a lot of good ideas, but I would like to see more
details. I think it would be good to take feedback from the industry and update
the information in it. At the abstract level, I think it's a pretty good vision
paper. I think overall it's a good initiative.