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Cambridge Analog Technologies is a provider of
high-performance, high-precision, ultra low-power analog IP that is sold to
designers of mixed-signal SoCs. It is challenging to design and verify this kind
of IP in the first place, and the company faces the additional challenge of
making it easy for its customers to integrate and verify the IP in the context
of the SoC.
In the video interview embedded below, Kush Gulati, Cambridge Analog Technologies CEO,
talks about his company's offerings, the need for integration-optimized IP, and
what verification his company does and what its customers need to do. This
interview took place at the Cadence booth at the recent Design Automation
If video does not launch, click here
Here are a few additional points not included in the video
clip. Gulati said his company eases integration challenges by providing
integration guidelines, extensive support, and training, with regular meetings
"all the way to GDSII." He noted that getting analog IP to work in noisy
digital SoCs is a major challenge, and that analyzing noise effects requires very
long simulations. While much progress has been made with simulation speed, more
is always needed. Substrate modeling is also becoming an important capability.
One point that emerged during this interview is that
integration-optimized IP, a concept discussed in the EDA360 vision paper, needs to be
developed for analog as well as digital blocks. In fact it may be even more
important for analog, given the difficulties of integration into mostly digital
SoCs. As Gulati said in the interview, "I think EDA360 is a great concept,
inasmuch as it takes into account the ecosystem of SoC manufacturers and IP
providers and EDA...I think it definitely can apply to analog/mixed-signal as