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Given increasing design complexity and skyrocketing costs, EDA standards have never been more important. As noted in the EDA360 vision paper, a standards-based ecosystem is absolutely essential if we're going to design the hardware and software that's needed to support tomorrow's creative software applications.
Fortunately, 2010 was a year of substantial progress in standards development, with the promise of more to come in 2011. This is the first of a two-part blog posting that updates some of the more active EDA standards efforts in 2010 and 2011. This first part covers Accellera and the IEEE, and the second part looks at Open SystemC Initiative (OSCI) and Silicon Integration Initiative (Si2) standards efforts.
First, I'll cite three 2010 high points noted by Stan Krolikoski, group director of standards at Cadence:
Here are some updates on specific Accellera and IEEE standards efforts. Cadence is actively participating in most of these efforts.
Accellera IP-XACT - This standard describes a meta-data documentation format for packaging, integrating, and re-using silicon IP. 2010: Accellera formed the IP-XACT technical committee, and the IEEE 1685 IP-XACT standard became available for free download. 2011: Tutorials and training to encourage usage, and enhancements to the IP-XACT schema with standard vendor extensions.
Accellera SCE-MI - The Standard Co-Emulation Modeling Interface supports the combined use of simulation and emulation. 2010: SCE-MI 2.1 was passed to the Accellera board for approval. It extends function-based interfaces and adds a pipe-based interface. 2011: Tentative plans to work on extensions that would provide a subset of OSCI TLM 2.0 capabilities.
Accellera UCIS - The Unified Coverage Interface Standard seeks to establish interoperability among verification coverage sources. 2010: Committee deep in technical discussions. 2011: Committee hopes to release UCIS 1.0 standard.
Accellera UVM - This is a crucial standards effort that enables interoperability among verification IP and tools. 2010: UVM 1.0 "early adopter" release based on Open Verification Methodology (OVM). 2011: Release of much-awaited UVM 1.0 is expected early in the year. It adds a register package, run-time phasing definition, and support for OSCI TLM 2.0.
IEEE 1076.1 defines VHDL-AMS, the analog and mixed-signal extension to VHDL. 2010: Initial investigations into revised standard. 2011: Work will begin towards revision that will add IP protection, enhanced VHPI programmatic interface, table-driven modeling, frequency domain modeling, and other features.
IEEE 1647 is the e verification language standard. 2010: A new LRM containing updates such as named checks, named constraints, real numbers, type constraints, and default method calls was submitted to the IEEE for balloting. 2011: A new standards revision is expected early in the year.
IEEE 1666 is the home of the SystemC language standard and is chaired by Stan Krolikoski. 2010: Language reference manual for P1666-2011 prepared and submitted for review. 2011: The P1666-2011 standard is expected to be through the IEEE approval process by mid-year. Features include inclusion of the OSCI TLM 2.0 standard, an elaboration of the OSCI TLM 1.0 message passing semantics, a process control extension, and clarifications of the previous standard.
IEEE 1734 defines a standard XML format for IP quality information. 2010: Technical efforts were completed, and balloting group was formed. 2011: Balloting is likely to start in mid-January. Interested parties are welcome to sign up; for further information, click here.
IEEE 1735 is working on an IP encryption and rights management standard. 2010: Ongoing work on interoperability to allow the exchange of encrypted IP among vendors. 2011: Expect "best practices" document to be balloted.
IEEE 1801 is the home of the UPF power format. 2010: IEEE 1801 standard published. 2011: Clarifications to standard published in 2010.
There's more...stay tuned for part 2!
While it's Xmas, I also wish that all these standards should help EDA users with something. But truth to be told - they don't!
EDA vendors are still mired in 'creating a competitive advantage/ lock-in scenario with their customers'.
Despite this plethora of standards the key critical aspect of full compliance to the syntax and especially the semantics of a standard is completely lost to the EDA industry at large.
Example: IEEE 1801 is a pain for users of multiple tool vendors. Yes, EDA folks, there are still people out there who do not have a single vendor environment!
VMM, OVM, UVM --> what's next GVM - the Galatic Verification Methodology? or better the GUM - the Great Unifiying Methodology?
EDA vendors create standards by numbers, as if incentives are given out.
And for me the worst aspect of it: the EDA user companies even participate in this sharade! Instead of driving these standards into the EDA industry, we are led like sheep and let us put into political camps when it comes to voting.
Every tool interprets the same standard differently. Is this by intention/ by design of those EDA vendors? One get's the feel that this is all on purpose.
So my Xmas wish: the EDA industry to GROW UP above and beyond these operational tactics of 'differentiating' through different interpretations of the same standards.
GROW UP and comply fully to the established standards.
GROW UP and compete on features and methodologies, not on standards.
Such an approach really would advance the state-of-the-art of the industry, every other effort is just waste!
Richard, on a personal note: I really appreciated your articles as an independent journalist. Now as a paid spokesperson of Cadence ...