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Metric-driven verification and constrained-random stimulus generation have greatly eased digital functional verification, but have rarely been applied to analog IP or mixed-signal SoCs. That may change with a proposed methodology called Universal Verification Methodology-Mixed Signal (UVM-MS), which will be described in a DVCon paper March 1 presented by Cadence and LSI Corp.
UVM 1.0 is an emerging verification interoperability standard that is soon to be released by Accellera. The Cadence/LSI work on mixed-signal metric-driven verification started with the Open Verification Methodology (OVM), which was the basis of UVM. An SoC Realization track paper at CDNLive! Silicon Valley last year, OVM-Based Verification of Analog IP and Mixed-Signal SoCs, offered a preview of what will be presented this year at DVCon.
The DVCon paper, titled UVM-MS: Metrics Driven Verification of Mixed Signal Designs, is authored by Neyaz Khan and Yaron Kashai of Cadence and Hao Fang of LSI Corp. I recently talked to Neyaz and Yaron to learn more.
Metric-Driven for Analog
Metric-driven verification (MDV) provides a systematic approach to verification that captures intent with an executable verification plan (vPlan), automatically generates test stimulus, and tracks the progress of verification through coverage metrics. This makes it possible to determine when high-quality verification closure has been achieved. An MDV diagram is shown below.
So why apply this approach to analog/mixed-signal? Neyaz noted that the analog content of SoCs is growing, and that the quality of verification has become a concern, especially at the interfaces between analog and digital. "There has been a lot of progress in the past 10-15 years in applying MDV to the digital side, but nothing like that has happened on the analog side," he noted.
The UVM-MS methodology primarily concerns functional coverage, which can provide measurements of parameters such as frequency and gain. For example, you may be looking at a variable gain amplifier and trying to verify that the output gain matches the spec. After generating stimulus to test the amplifier by sweeping the input frequency over the allowed range, you can then use functional coverage metrics along with automated checkers to make sure that the desired range of the gain has been completely tested.
To allow analog functional coverage, the methodology uses the e language to create "signal ports" that sample analog parameters. Due to some limitations in SystemVerilog, the UVM-MS methodology is currently based on e, but the long-term goal is to work with SystemVerilog, Neyaz said. While Cadence offered MDV well before UVM, the new methodology leverages UVM because of its broad vendor acceptance as an industry standard.
Supporting Existing Styles
Analog simulation is traditionally interactive and slow, while digital is batch and fast - how can designers bridge that gap? The UVM-MS methodology supports all analog modeling styles including Spice, Verilog-AMS, and real number models, allowing a speed-versus-accuracy tradeoff. Low-level analog operations are facilitated by a Verilog-AMS layer that runs underneath the hardware verification language code. A library of components supports commonly used interfaces between analog signals and testbench functions.
The overall verification methodology, Yaron said, "is pretty much the same as doing MDV with digital, but certain things need to be done to facilitate the integration with analog. The model has to be tied to the testbench in a certain way. One has to structure the verification environment slightly differently for analog design. You need to instantiate some of these [digital] blocks to talk to analog ports and drive some analog signals."
Neyaz noted that the methodology does require teams to invest more effort in analog IP verification. "Keeping in mind that the IP is designed once and used in multiple chips, having high quality IP is a very good investment," he said. The paper details how a current design from LSI Corp. was used for proof of concept.
The DVCon paper is part of session 3.4, which starts at 8:30 am Tuesday March 1 at the DoubleTree Hotel in San Jose, Calif. Conference registration is available at the DVCon web site.