Get email delivery of the Cadence blog featured here
Mixed-signal verification is a tough challenge, and much of the difficulty lies with models. How can engineers choose the right modeling approach and guarantee that models accurately represent the silicon? A session at last week's (Feb. 17) Cadence "Tech on Tour" seminar provided some answers.
Cadence last week launched a series of "EDA360 Tech on Tour" Silicon Realization/Mixed-Signal R&D seminars. These full-day events will take place at several North American locations this week (listed below), and in Europe and Asia in March. Information and registration is available here. In addition to AMS behavioral modeling, topics include:
The session I attended, AMS Behavioral Modeling, was presented by Walter Hartong, staff product engineer at the Cadence facility in Munich, Germany. It was packed with good information and presented to an attentive audience that mostly filled a large auditorium at the Cadence San Jose headquarters Feb. 17.
The Mixed-Signal Verification Dilemma
What mixed-signal designers really want, Walter said, is fast and accurate simulation of a full chip with the package. But SPICE can take weeks to finish, and digital simulation is fast but doesn't consider analog effects. You can run a small block on SPICE, but that doesn't tell you if the block works properly in the context of the chip.
There are several styles of behavioral modeling that can apply to mixed-signal designs. Walter identified three, all of which are supported by the Cadence Virtuoso AMS Designer:
So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Also important is the modeling effort. Here we can see that conservative models require the most amount of effort. "You can potentially spend days, weeks, months to develop good behavioral models," Walter said. Wreal models are relatively fast to develop because they're less detailed. An important rule of thumb: "Model what you need, not what you can."
How Do We Know the Models are Good?
Behavioral models are worthless if they don't accurately represent the silicon. Continuous model validation is necessary, Walter noted, because both designs and models change over time. One small change to a model or the design could invalidate the model.
Walter ran through a demo of amsDMV, a Cadence Virtuoso model validation tool mainly targeted at analog/mixed-signal. It provides an automated way to quickly run regression tests, but it's not a replacement for an analog designer who can do a detailed model validation. "Don't be scared it will replace your job," Walter said. "It doesn't know the details of the model or the circuitry, it just raises a flag if the simulation results are different from what they should be."
If this one session (out of 10 in the full-day seminar) is any indication, this is a very useful seminar series. It repeats in Boston Feb. 22, Austin Feb. 23, and Irvine, CA Feb. 24.
Related Blog Posts
UVM-MS -- Metric-Driven Verification for Analog IP and Mixed-Signal SoCs
Advanced Mixed-Signal Designs Demand a Unified Methodology
Behavioral modeling lets you choose your accuracy/speed trade-off level. You can get the same accuracy as Spice if you want but with a more efficient model - simulating transistors is an unconstrained problem, simulating specific circuits is constrained and mathematically more stable.
Really you should only use Spice to characterize cells, and for any higher level activity you use the behavioral models.
Behavioral models can include assertions to warn you if you abuse them.
Thanks for the article. As previous commenter pointed out; performance gain is achieved by increasing the abstraction level, simply by eliminating costly model evaluations. However, this is also a trade-off for accuracy.
Thus, I find perf-accuracy graph misleading. Generally, fastspice simulators perform better than Conservative Behavioral model simulations /w fastspice. This is due to the fact that, fastspice applies circuit partitioning/device matching techniques to speedup the simulation. This advantage is lost when conservative behavioral models are used since simulators do not know how to handle the detailed behavioral model efficiently.
I think that behavioral analog models, as you pointed out, are not useful if they are not accurate and can loose their advantages(in terms of performance of simulators and effort to develop them) if they are too much accurate.
Actually if the analog models should represent every aspects of analog circuits they can' t be really advantageous!
I think that the real benefit of analog models is that they can be very accurate in the operating points(areas) of interests of analog circuits and very simple in other operating areas that are not of much interest (while spice models maintains the same accuracy, or better the same computational load).
So in order to gain performance advantages one should model with a high accuracy only the operating points in which one could use that models(for example in full chip simulations each analog circuit has a specific way in which is used).
For reducing the effort to spend for modelling, common strategy for every category of circuit could be developed to model beavior of interests.
For example all regulators could use the same modelling strategies in their operating point ( based on interpolation of data taken from spice sims etc etc ).
The same could apply for charge pumps, input output buffers, pll, dll etc etc.