Get email delivery of the Cadence blog featured here
Is the EDA industry "responsible?" Not unless EDA tools provide enough automation to keep design costs low, according to Gary Smith, chief analyst at Gary Smith EDA. Speaking at his annual industry forecast talk June 5, on the eve of the Design Automation Conference (DAC), Smith said that EDA tools need to provide more productivity so that engineering head counts can be lowered.
First, the good news. Smith expects EDA industry revenues to reach $4.89 billion in 2011, just slightly over the $4.87 billion reached in 2007 before the recession took hold. And it's all uphill from here, reaching over $6 billion in 2015. "The Great Recession is over," Smith proclaimed.
But EDA also has a responsibility, Smith said. Borrowing from a speech given by venture capitalist Lucio Lanza, Smith said that "EDA is responsible for developing the design tools that enable the IC design process, at a design cost that allows the ecosystem to operate at a profit." Profit, Smith noted, "is key and unfortunately isn't happening right now, and that's why we're seeing a lot of problems in the industry." (A similar idea can be found in the EDA360 vision paper, which discusses a looming "profitability gap" among IC and system design companies).
Too Many Engineers?
Smith immediately clarified that he's not talking about the cost of EDA tools. That's "lunch money." What he's talking about is the level of automation. The costs that must be reduced, he said, lie in the number of engineers required to do the design.
If we can keep the cost of designing a system-on-chip (SoC) below $25 million, the VCs will start funding semiconductor companies again, Smith said. If we let the cost rise above $50 million, even the IDMs won't be able to do many designs. Unfortunately, that's the direction we're heading. The cost for SoC hardware design is typically over $25 million and rising, and software may add another $56 million on top of that. "We have to change that curve," Smith said.
The hardware design team size today ranges from 100 to 200 engineers. For 104 million gates, this number "should be" 30 engineers, Smith said. We know it's possible because some companies are doing this today - but most are not.
By the Block
The "ideal" number of blocks in a design is 5, and anything over that slows the design and drives up costs, Smith said. But usually there are 25 to 35 blocks. This is where platform-based design comes in. If a 100 million-gate chip is based on a 90-million gate platform, only 10 million new gates need to be designed, and that can be handled with 5 two-million gate blocks.
How many gates should an EDA tool handle? At least 4 million gates, and ideally 20 million gates, Smith said. (He didn't say which type of tool). EDA's biggest problem today? "We still have far too many R&D engineers who don't have the slightest idea how design engineers use their tools."
Smith said EDA providers need to develop the productivity tools needed to keep engineering head count down, and get involved in the software productivity problem. Traditional embedded software development companies "are not handling the load," so EDA companies will have to take this on also, Smith said.
Smith's key takeaway is the following statement: "The EDA industry is responsible not only for enabling the design process. It is responsible for developing a level of automation that allows the design process to be affordable."
It doesn't get much more "bottom line" than that.
ADDENDA: A Musical Interlude
As the DAC show floor opened Monday morning, Gary Smith sang the blues -- literally. To watch a short video of the Full Disclosure Blues Band, click here.