Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
So far the move to lower semiconductor process nodes has continued unabated, but the upcoming 20nm node is causing a lot of concern. Lithography is so challenging that extra masks (double patterning) will be required. Will designs be technically and economically feasible? Panelists at the Design Automation Conference (DAC) June 6 said "yes," but acknowledged that the challenges are very real.
A Cadence-sponsored panel at DAC, titled "Getting a Jumpstart on 20nm," explored the challenges of this emerging process node in depth. Panelists (shown left to right below) included:
Setting the tone for the discussion, Handy commented that "20nm is really a very different process node. Some say it's shaking the very core of semiconductor design. You're going to see new processes and techniques." Following are brief answers to some of the questions posed to panelists.
Q: What's the single most difficult thing about 20nm?
Segars: "What bothers me most is pure economics. With double patterning, masks, and NRE costs, will it make economic sense to design at 20nm?"
Hunter: "The economics are challenging, but customers are asking for it sooner, not later. There's still a lot of interest in getting more performance out of 20nm. The challenge is bringing everything together fast enough. A lot of development work on the process side and the EDA side needs to be done."
Magarshack: "We could spend five years optimizing libraries and design rules, but we have to get going. I think the main challenge is to find a way to stop negotiating design rules."
Hsu: On the business side, "EDA is hard-core software development that takes a lot of resources." On the technical side, turn-around time will be the challenge. "We will figure out how to make use of the process. The question is how well we can take advantage of the process."
Q: At 20nm we're doing high-k metal gates (HKMG) and low-k metal interconnect. What do we need to do to avoid problems?
Segars: "We're trying to abstract out all that horror of high-k, low-k, so designers only need to worry about the architecture and the implementation."
Magarshack: High-K, low-k combination is very positive. High-k transistors gives performance boost of at least 20 percent. Low-k wires lower capacitance, providing lower power or higher performance.
Hsu: "As long as you can make the process work, and the libraries work, we will make [EDA] work." But early collaboration is crucial. Cadence started working on 20nm much earlier than with other process nodes - the effort started 2 ½ years ago, in fact.
Q: Double patterning gives you two times as many transistors per a given lithography, but it needs highly regular structures. What are the challenges in using double patterning?
Segars: "It certainly imposes new design rule constraints. You have to make sure shapes can be split into two masks. As library guys, we try to abstract away those details."
Magarshack: "We need to collaborate early with the library and process guys to get a better compromise than a simple, pushbutton solution that would leave something on the table in terms of density and power."
Hsu: "All of our partners use slightly different approaches. Some use double patterning, some don't, some add different variations." Also, double patterning has an impact on electrical characteristics and variation that must be considered.
Q: Is double patterning necessary at 20nm?
Hunter: Samsung has chosen to optimize its process for double patterning to get better density. Going below an 80nm pitch requires double patterning. We have chosen to go with a 64nm pitch. This will provide about a 35 percent performance improvement from 28nm to 20nm at the same leakage.
(There was no specific question about 3D-ICs, but several perspectives were given).
Hunter: 3D-IC is very complementary to 20nm and we are investing in it heavily as well. High voltage or analog circuits may not need the shrink path of digital.
Segars: "We've tried to do every type of circuit by putting all transistors on one die. If we can split up the transistors into 65nm analog/mixed-signal and optimize digital transistors differently, this [3D-IC] technology could really help."
Magarshack: "So far we have not found an economically viable product for TSV [through-silicon via]. We're still at LPDDR2 and LPDDR3 rather than jumping into wide I/O."
Having listened to the panel, I have no doubt that foundries will offer a 20nm capability and some people will use it. But how many and how soon, and how well will libraries and tools take advantage of the process? Very early and deep collaborations, such as those undergone by Cadence and the other companies represented in this panel, are the key to 20nm success.
Kudos to Richard for accurately capturing the important points of the panel.