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Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the Cadence booth at the Design Automation Conference (DAC). Separately, I interviewed Kuo at DAC, and what follows are excerpts from a conversation that included such topics as IP integration, power estimation, power network design, dynamic voltage and frequency scaling, and the use of the Common Power Format (CPF).
Q: Alex, what kinds of chips are you designing at Global Unichip, and what are the challenges?
A: We take a lot of specifications from different customers. Usually our major challenge is gate count. When we come to 40nm the gate count increases tremendously. Almost every 40nm design we've seen so far uses a hierarchical flow. You've got to put more and more on the chip to justify the cost.
Power has also become a key concern. Before, if the customer was using a generic process power was less of a concern - the major concern was speed. But recently even 40G process customers are concerned about power.
Q: What are your biggest challenges today in power management, in both architecture and implementation?
A: One of the architectural challenges is IP integration. We need a lot of different IP for different functions, and it makes our clock tree very complicated. Power modes increase a lot. When we combine different signoff corners, the signoff period becomes very long - it's very painful.
On the implementation side, I think the challenge right now is in [power] estimation. Cadence is putting a lot of resources and efforts into managing the implementation flow.
Low power makes test more complicated. Power could be off or on. You're supposed to have memory that is always on, but we had an issue where we lost the state. A lot of problems can happen.
Q: How does low-power design get more complicated below 40nm?
A: At 28nm, power network design will be very critical. I think we will need a correct-by-construction feature for the power network. Right now we just use manual fixing. We're going to need some tool help.
Q: One of the chips you described in your Cadence presentation used dynamic voltage and frequency scaling (DVFS). What are the pros and cons?
A: DVFS causes a lot of complications in signoff procedures because you have different voltages and different on-off situations. But there are not many methods we can use to lower dynamic power. DVFS is a very useful method to lower dynamic power. So if a design has severe dynamic power concerns, we have to consider it.
Q: How do you use CPF in your low-power designs?
A: The customer designs the CPF file and we use CPF as a constraint. When they hand over their data, it's not only netlist constraints but also CPF. When we run Cadence tools to do power checking, we make sure we use CPF.
We use the Encounter Digital Implementation System, VoltageStorm, and Encounter Timing System, and one of the most important capabilities in the flow is CPF. We don't have to deal with point tool requirements - we only need to maintain one CPF file.
Q: What advice would you give to designers about low-power, advanced node design?
A: You need to understand the low-power technologies available right now, and then based on your spec, decide which techniques to apply. There are a lot of different technologies, and many will bring additional complexity.
(Note: For more details about Global Unichip's low-power flow, see Qi Wang's blog post.)