Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Two leading EDA industry standards organizations - Accellera and the Open SystemC Initiative (OSCI) - announced their intent to merge into a "new organization" today (June 22, 2011). The move will bring most "front end" EDA standards (RTL and above) under one roof, and potentially make it easier to align SystemC and the OSCI TLM modeling standards with other industry languages and standards. The result: a stronger EDA standards effort across multiple levels of abstraction.
The union will help unite standards activities at the RTL, system, and software levels, said Mike Meredith, OSCI president. "All of these [levels] are having to come together to get chips out in a reasonable time frame," he said. "As design activities start to converge, the need for tightly coupled standards in all these areas increases."
"The entire system really needs to be designed with hardware and software in mind," said Shishpal Rawat, Accellera chair. "More and more, we have to figure out how to get the software done in a manner that benefits the industry with respect to turnaround times and common standards."
There's a precedent for this merger. Last year the Spirit Consortium, creator of the IP-XACT metadata standard for IP integration, merged into Accellera. As a result, Rawat said, IP-XACT is being adopted in the system design community "in a much broader way," with many downloads of the standard since it became part of Accellera.
However, today's merger does not appear to be about one organization merging "into" the other. Rawat said that Accellera and OSCI are forming a single organization, and are currently discussing what the final form and shape will be. Meredith said that the boards of Accellera and OSCI have each formed a subcommittee to thrash out the organizational details. One question that remains is what the new organization will be called.
SystemC and UVM
The Accellera-OSCI merger opens the door to some interesting possibilities, especially with respect to the Universal Verification Methodology (UVM) and SystemC. At a "town hall meeting" at the DVCon conference in February, organized by Accellera and OSCI, there were several calls for a UVM-SystemC capability. Said one audience member: "we need to define what methodology to use with SystemC, and how to bring it back to RTL. An open-source implementation of UVM for SystemC would really help out a lot."
"Clearly, multi-language support is something we need to work on from a UVM perspective," Rawat said. He also noted that there needs to be some "common ground" in the analog/mixed-signal extensions to SystemC and Verilog that OSCI and Accellera are working on, respectively.
"We observe that more and more activity in SystemC is becoming tightly linked with implementation activity at the RTL level, and we need to bring this together," Meredith said.
According to Stan Krolikoski, group director of standards at Cadence, combining Accellera and OSCI may help accelerate some existing standards efforts and foster new ones. "SystemC is getting more and more aligned with other design languages, so it makes perfectly good sense," he said. He noted that TLM 2.0 has become part of the Accellera Universal Verification Methodology (UVM), that some designers have expressed interest in UVM-SystemC and other languages, and that many designers would like to be able to move from SystemC to SystemVerilog in a more transparent manner.
After the Spirit Consortium moved into Accellera, Krolikoski observed, the UVM register team needed to work with the IP-XACT team in order to have some consistency in register descriptions. This was easy because both teams were part of one organization. With two different organizations, IP rules, and management, this kind of synergy would be much more difficult, Krolikoski noted.
Ongoing Accellera activities include the following:
Ongoing OSCI activities include these working groups:
It will be interesting to see how these activities converge - and what new initiatives arise.