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Engineering change orders (ECOs) are inevitable, but the need to restart chip layouts is not. Engineers at Cisco Systems' ASIC design center in Ottawa, Canada, are having good success with complex functional ECOs using a combination of manual scripts and the Cadence Encounter Conformal ECO Designer, according to Sid Allman, hardware engineering manager at Cisco.
In the following video interview from the recent Design Automation Conference (DAC), Allman discussed the challenges of ASIC design at 40nm and below (too many corners, signoff takes too long). He noted, however, that ECOs do not get more burdensome at lower process nodes, provided one uses a "structured" approach. He then described how Cisco uses both manual scripts and automation with Conformal ECO to implement ECOs, how designers can find the best possible RTL change, and why equivalence checking provides a needed "foundation" for quick ECOs.
"We've been very successful at implementing larger ECOs very quickly then we ever thought imaginable," Allman said. You can't argue with success.
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I like the low key interview style but the background was noisy and distracting and a whiteboard or one or two illustrations would have been handy. You should setup a small studio (8x8 section in your booth) where it would be a little quieter and the person interviewed could sketch one or two simple diagrams to provide context