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What are the most important system on chip (SoC) interfaces that design and verification engineers need to understand? A "top ten" list presented at the August 25 Verification IP (VIP) seminar at Cadence included some old standbys and some new and emerging interface specifications. The list was provided in the opening session of the seminar, which provided an in-depth look at the Cadence VIP Catalog and presented case studies showing the verification of AMBA4 ACE, PCIe Gen3, USB 3.0, and DDR4 interfaces.
In the opening session Tom Hackett, Cadence product marketing manager for VIP, cited "two revolutions driving massive change in the electronics ecosystem." One is the Mobile Revolution, in which mobile devices are replacing PCs. Part of this revolution is what Hackett called "the triumph of the app," including media apps, business apps and physical apps. The second revolution is the Cloud Revolution, which is "providing the hub for the mobile world" in two ways - by allowing the on-line storage of data, and by providing access to software running on remote servers.
Hackett noted that system interfaces play a key role in both the mobile and cloud markets. "The biggest single challenge impacting mobile and server projects," he said, "is your ability to master the verification of these interfaces. This work will directly influence the end user's experience."
The 10 Essential SoC Interfaces
Hackett divided his "top ten" list into two portions. The first five interfaces, shown below with his comments, enable mobile technology. Included here are new and emerging interfaces such as MIPI LLI, LPDDR3, and UFS.
The next five interfaces enable cloud technology.
"Your job as a verification engineer," Hackett told the audience, "will be to master these interfaces." VIP can help, he said, by automating the verification of standard interfaces, checking protocol compliance, verifying host and device designs, and generating and driving test sequences. The newer protocols are so complex that home-grown VIP could take engineer-years of development.
Hackett's presentation also discussed the Cadence VIP Catalog. The following two figures show VIP components (blue) and memory models (yellow) available in the catalog. These VIP components and models run on all major simulators. Further information is available here.
I was having lunch with a former co-worker of mine yesterday and he was telling me that he'd interviewed for a position where he was asked about his knowledge of 10 different interfaces, including many of the ones mentioned above. It seems that you need to be multi-lingual these days to get a job.
Good point Muhammad. The cost of internally-developed VIP is actually quite high. Customers have quoted "man-years" of development time for complex interfaces and that doesn't include the cost of cultivating dedicated protocol experts in the first place. We do see more customers starting to look at these internal costs and being more open to external VIP, especially when they can get production-proven VIP off-the-shelf. That lets them focus on debugging their chips instead of debugging internally-developed VIP.
I agree with interfaces but I have reservation on VIP.
I have been working in the design verification for more than a decade. VIP has very low penetration in the real DV environments due to its cost. Companies are willing to pay their engineers to develop custom solutions but never pay to the VIP vendors.
Thanks for the perspective. The "top 10" will always be a moving target, but I chose Ethernet 40G/100G in the networking space for its potential to further consolidate storage area networks onto the Ethernet backbone. As for other top 10 candidates, Thunderbolt is one we are keeping a close eye on.
This is a good list to start with but I wonder if the Cloud computing interfaces may undergo a change. As the Network and the Server markets merge to meet the cloud requirements we are seeing Interlaken and QPI as emerging interfaces which will complement these.