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Printed circuit board design isn't what it used to be. To successfully design today's high-speed boards, designers must understand transmission lines, signal integrity, crosstalk, power delivery, differential signaling, and electromagnetic interference (EMI). In the following Q&A interview Robert Hanson, a PCB design and signal integrity expert with over 40 years of industry experience, discusses these challenges and describes best practices for successful high-speed board design.
Hanson, who teaches seminars and consults with companies all over the world, is teaming up with Cadence to offer a series of 5-day seminars on high-speed digital PCB design and EMI. Seminars will be held at Cadence facilities Sept. 19-23 in Austin, Texas; Oct. 17-21 in San Jose, Calif.; and Nov. 7-11 in Chicago, Ill. These hands-on seminars will include demonstrations of Cadence Allegro and OrCAD PCB design and simulation tools. A recent blog post describes the seminars in more detail.
Q: Robert, what are the most significant problems that you are seeing in PCB designs these days?
A: It's dependent on the design - whether it's high speed/low speed, high edge rate/lower edge rate, a simple PCB or large backplane design. However, some of the glaring problems are transmission line reflection due to the capacitive load; ground bounce; crosstalk between violent aggressors (like CMOS) and sensitive victims (like ECL/PECL and analog); bypassing and power delivery; common mode differential pair problems; and high speed clock loading.
Q: How fast are the fastest boards you are seeing? How complex in terms of components and pins?
A: Several students in my classes are designing backplanes, servers and blades that have clock frequencies up to 11GHz. I consulted for a company that built a backplane with 65 BGAs having over 600 balls each, 34 layers and over 58K solder joints. The fastest digital board (not microwave) was an aerospace design running at 43 GHz. Regarding components, there is a BGA graphics processor with a clock speed of 5.6 GHz that has over 3400 balls. How would you like to reflow solder that one?
Q: Day 1 of your seminar covers transmission lines. What are the most important points you'll be making?
The most significant thing would be defining the cutoff conditions to determine when a land trace acts like a transmission line versus a lumped circuit. This will determine to a large degree the termination scheme that will be used to minimize reflection. It is also important to define skin effect, dielectric loss and proximity effect. The interesting point about proximity effect is that if the spaces are just a fraction of the land width (like 5 to 1) this will create more signal loss than skin effect, dielectric and surface roughness combined.
Another subject is signal delay for microstrip and stripline. With microstrip, the delay is not the same for bare, solder mask covering and conformal covering (encapsulation over the solder mask). I'll also talk about providing the analysis for characteristic impedance and delay expressions for microstrips, buried microstrips, striplines and differentials.
Q: What design techniques are needed to keep signal integrity under control?
A: Excellent communication between the EE design engineer, the PCB design engineer, the test engineer and manufacturing engineer is critical. Also, close coordination with the bareboard vendor and the EMS supplier is essential. The inputs from all of these will influence the best design techniques for achieving signal integrity. It is very important to conduct digital simulation (as with Cadence Allegro SI) and EMI/EMC simulation. The more up front the potential problem identification, the less debug time, the fewer problems during compliance testing, and the quicker the time to market.
Q: What crosstalk problems are you seeing in high-speed designs (Day 2)?
A: High density board layout is very challenging. I have seen designs where 2s and 2s [2 mil-in wide land traces and spacing] are being used due to density/packaging restrictions. Interference between CMOS/TTL high edge rates and ECL/PECL is another problem. Yet another major concern is sensitive analog circuits in close proximity to the fast edge rate digital signals. This is where guard traces around the analog traces become effective.
Q: How does crosstalk impact layer stacking?
A: To control crosstalk there has to be a distance between the aggressor and the victim versus the distance to the reference ground plane or power plane. Therefore, the tradeoff in many cases is how do I minimize my stackup layers (which is a cost consideration) versus controlling the crosstalk, and also the characteristic impedance, which is also a correlation between trace width and distance to the reference plane (or planes as in striplines).
As each new design is released there is typically a higher clock rate with higher edge rates, more signals per IC package, and a need for higher density that exacerbates crosstalk. In my estimation this will be one of the major challenges for the design community, as competition and cost considerations will highly influence the layer stacking.
Q: What do designers need to do to ensure adequate power delivery within a specified power envelope (Day 3)?
A: In one word it's inductance. Designers need to identify how much inductance is inherent in the mounted capacitor loop and the ESL [equivalent series inductance] of the capacitor. The characteristics of the power and ground planes are also critical. Today cores are being produced with less than 1 mil-in of dielectric thickness. If these are used, they will they enhance the power delivery, but at what cost?
Designers must know the bypassing capability of their output drivers. The only way to overcome SSO [simultaneous switching output] is at the die level. So designers need to provide the proper dq/dt at the needed IC pin at the right time.
Therefore, one must know the maximum level of power delivery noise allowed in the overall noise budget. With that knowledge the best strategy is to provide the correct IC die capacitance, inner plane capacitance, discrete capacitance and capacitor types (such as X2Y, Y cap, reverse electrode) to achieve this goal. Another factor, especially as frequency increases, is the anti/parallel resonance considerations that may require breaking up the capacitors into banks with different ESRs [equivalent series resistances] and different loop inductances.
Q: What "best practices" do you advocate for differential signaling and clock distribution (Day 4)?
A: Probably the main concern is differential unbalance caused by the two lines not being the same electrical length. This causes common mode and is the main reason differentials can fail EMI radiation. Another consideration is to assign the more sensitive pairs as striplines. Avoid broadside layouts, that is, make them be edge to edge. Broadside layouts in many cases can render the design inoperable due to returning currents being contained on different ground planes, or possibly power planes, which can cause the receiver to see a totally different noise spectrum on its inputs.
Q: When does EMI become a concern in PCB design, and what do designers need to know (Day 5)?
The two big concerns are radiated emissions and ESD [electro-static discharge]. All radiated emission formulas have both edge rate and frequency as two of the parameters. Therefore, many of the signal integrity rules also apply to EMI. The main cause of radiation from circuit boards is the size of the antenna loop -- that is, the pathway the current takes to the load and the direction/pathway that it takes to return to the VRM module. The more area this entails, the more radiation.
The designer must know the ESD pulse edge rate, which in turn will define the protection device (TVSS) or the filter. Another concern today is the ever increasing frequency, higher clock rates, and power dissipation in the design. Designs are becoming denser with more power dissipation. Due to the higher clock rates the apertures are decreasing in size to minimize harmonic radiation, meaning that the wavelengths are becoming shorter. However, with smaller apertures the design is much less efficient in allowing heat to escape the enclosure. This is one of the major concerns in EMI mechanical compatibility design.
Q: What will each day of the seminar cover, and how will Cadence tools be demonstrated?
A: Each day at the conclusion of the training session, Cadence engineers will demonstrate examples of the lecture material. This will provide the student with real world examples of the methods used to design correctly. The following provides an itinerary of the courses.
TRANSMISSION LINES (Day 1) - Fundamentals of transmission lines including stripline vs micro-strip. Cadence Demo: Pre- and post-route SI analysis using ideal and lossy transmission lines.
CROSSTALK (Day 2) - Stack-up optimization and forward/reverse crosstalk. Cadence Demo: Pre- and post-route crosstalk analysis as well as crosstalk estimation.
POWER DELIVERY (Day 3) - Proper use of decoupling capacitors and identifying power plane resonance. Cadence Demo: Allegro PCB Power Delivery Network (PDN) analysis
DIFFERENTIAL SIGNALING (Day 4) - Loosely vs. tightly coupled differential pairs; clock distribution. Cadence Demo: Tandem and broad-side differential pair routing and analysis.
EMI/EMC (Day 5) - Source, path, and receptor as well as how EMI/EMC tests are conducted. Cadence Demo: EM control rule checking and EMI net analysis.
Q: What's your most important advice for clients working with high-speed digital boards?
A: One could write a book on this, but to briefly state the advice: know the rules of high speed design, work as a team in the prototype design, simulate the design, and work closely with the bareboard vendor.
Note: If you're interested in the topics discussed here, there's nothing like a hands-on seminar to learn more. Each course can be taken on a standalone basis or combined as needed. You can read about the upcoming seminars and register here.