Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To get a handle on what's happening in DFT these days, I talked to Mike Vachon, group director of the Cadence Encounter Test product, as he was preparing for next week's International Test Conference (ITC) in Anaheim, Calif. Sept. 18-23, 2011.
"The complexity and the amount of effort that DFT and ATPG take is really growing quickly as designs move to smaller lithographies," Vachon said. He noted that companies are finding they need a lot more DFT expertise, and that DFT IP is becoming vastly more complex, leading to an increased reliance on EDA vendors to generate, validate, and insert that IP during the design process.
Don't Get "Stuck" at Lower Process Nodes
Until recently, designers have focused mostly on static, stuck-at-1 and stuck-at-0 defects. At 45nm, Vachon noted, delay faults begin to become important. At 28nm and 20nm delay faults dominate the defects that customers see. Delay faults (or transition faults) can result in "slow to rise" or "slow to fall" defects. "The tests required to detect those kinds of defects are complex, and they require at-speed test clocking," Vachon noted. "This drives the need for special test clocking IP during DFT insertion."
Further, Vachon noted, bridging faults are becoming more prominent at 28nm and below. These are defects that tie two wires together that should not be coupled. Thus, a new bridging fault model is required, along with related test vector generation.
Test compression, which results in test vector sets that can be applied in less time (and thus for less cost), has been around for some time. But it's becoming more critical at lower process nodes because the complexity of test vector sets is skyrocketing. Further, compression is difficult in low-pin count architectures, which are common in the "big A, little D" mixed-signal design world.
There are other concerns as well. Because test vector sets at 28nm and below are getting huge, ATPG for large SoC designs is slowing. It could take 3-4 weeks to generate test vectors for a large design, "not a manageable amount of run time," as Vachon said. And some IC design environments still wait until after synthesis to insert DFT structures. This results in problems with timing, power, and routability.
At ITC, Cadence will show how it is responding to some of these challenges. One response actually took place several years ago, when Cadence decided to move all of its DFT insertion and verification capabilities into the RTL Compiler synthesis tool. Thus, tasks such as scan chain insertion, compression, clock generation for at-speed test, and memory BIST are accomplished during, not after, synthesis. While ATPG occurs in the Encounter Test product, RTL Compiler leverages the ATPG environment to estimate test coverage and insert test points.
One new capability that Cadence will discuss at ITC is logic BIST. While BIST is frequently applied to memory, logic BIST saw most of its use 10 or 15 years ago, when it was used for processor design. But now - it's back! Vachon pointed to a "huge increase in demand" for logic BIST over the past year or two in the automotive market, as well as for some consumer products. (Cadence has manually generated logic BIST macros for a long time; what's new now is the ability to insert a standard macro as part of the synthesis process).
Another new capability is SmartScan, a very low pin count compression architecture that will be especially helpful for big A, little D designs. In this market segment, a device might only be able to spare 4 or 5 pins for test. SmartScan essentially puts a wrapper around an existing compression architecture that allows designers to control a test compression macro with a very small number of pins. Here is how it works in the RTL Compiler and Encounter Test environments:
Finally, Cadence is presenting an improved, distributed ATPG capability that runs in parallel computing environments. Vachon said that it can produce a 13X speedup with 16 CPUs, or a nearly 4X speedup with 4 CPUs.
Cadence at ITC
Cadence activities at ITC include:
Further information about these activities is available here.