Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
More than any other language standard, SystemC has made system-level design possible. It is the lifeblood of high-level synthesis, virtual prototyping, and transaction-level verification. Thus, the first IEEE revision of the standard in six years -- announced today (Nov. 10, 2011) as IEEE 1666-2011 -- is a milestone event for all who are using SystemC or may be doing so in the future.
The IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666 "Standard SystemC Language Reference Manual," and it is expected to be available early next year. Compared to the original IEEE 1666-2005 standard, the new standard has a number of clarifications and bug fixes, has been expanded to include the transaction-level modeling (TLM) interfaces developed by the Open SystemC Initiative (OSCI), and has added some important new language features such as the process control constructs noted below.
With IEEE 1666-2001, said Stan Krolikoski (right), chair of the IEEE 1666 Working Group and group director of standards at Cadence, "there is no question [SystemC] is a real standard." To gain even more international recognition, he noted, the SystemC standardization effort will now move on to the International Electrotechnical Commission (IEC).
Additions to the 2011 Standard
The OSCI TLM interfaces help enable interoperability and reuse for SystemC models. TLM 1.0 defines a standard set of APIs for transaction-level communications, but does not define the content of the communications. TLM 2.0 defines the content of transactions with a "generic payload" and also identifies two levels of transaction-level modeling - Loosely Timed (LT) and Approximately Timed (AT). The TLM nomenclature may be a bit confusing in that TLM 1.0 is not a direct subset of TLM 2.0.
In addition to adding the TLM interfaces to the LRM, the IEEE 1666 Working Group has clarified their descriptions and fixed bugs, Krolikoski noted. Now, he said, "it's in one spot, it's cleaned up and it is the official standard." While widely used today, OSCI TLM 1.0 and TLM 2.0 have not been IEEE standards until now.
There are other new features in the 2011 standard as well. One is process control constructs, which I blogged about earlier this year. In short, processes are basic behavioral entities in SystemC, but the 2005 standard lacked a direct API for controlling one process from another. The new process control constructs make it possible for one process to suspend-resume, disable-enable, or kill/reset another. This is useful for developing testbenches, modeling asynchronous resets or triggers, or simulating events such as a sudden power loss to a computer.
Process control constructs are based on a specification written by Cadence and submitted to OSCI several years ago. They are supported in the Cadence Incisive Enterprise Simulator. A 2009 Cadence paper describes further details about their use.
Cleaning and Expanding
Other new features in IEEE 1666-2011 include the following:
Beyond these new features, Krolikoski noted, were a number of small clarifications and bug fixes. "SystemC really took hold after its standardization in 2005, and there were lots of areas where there were questions, and in some cases bugs. We cleaned that up for 2011." Indeed, a lot of people read that 2005 standard. Krolikoski noted that over 50,000 copies of the 2005 LRM have been downloaded, thanks in part to a deal in which OSCI paid the IEEE so the LRMs could be downloaded for free.
IEEE 1666 is a corporate standard (one company, one vote). Members of the IEEE 1666 Working Group include Accellera, Cadence, Freescale, Intel, JEITA, Mentor Graphics, NXP, OSCI, STMicroelectronics, STARC, Synopsys, and Texas Instruments. The 2011 standard was a true international effort, Krolikoski said, and was almost all conducted by email, making it a true Internet-driven standard.
Congratulations to all whose hard work is reflected in the new 2011 SystemC standard!